Also known as: Power Modeling Engineer; Low-Power Architect; Energy Efficiency Architect; Power Management Architect
See this role on the SoC lifecycle or on the AMS lifecycle or on the AI accelerator lifecycle or on the Soft IP lifecycle
Owns the chip's power and energy budget from architecture through silicon, defining power domains, states and management policy so the product hits its battery life, thermal envelope or data-center TDP target. Turns power from a late surprise into a designed-in property.
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