Power-aware simulation

Notes

Missing isolation shows up as X-corruption propagating from a powered-down domain into an always-on one.

Overview

Power-aware simulation is functional simulation of RTL or a gate-level netlist that also reads the design's power intent, usually written in UPF, and models what happens when parts of the chip are switched off, isolated or held in retention. It is the main way teams check power-down, power-up and save-and-restore sequences before silicon. An ordinary simulation assumes every block is always powered, so it cannot catch these bugs.

How it works

The power intent file, defined by IEEE 1801 and known as UPF, describes the power domains, the supplies and switches that feed them, and the isolation, retention and level-shifting strategies at their boundaries. A power-aware simulator combines this with the RTL. When the simulation turns a domain off, its logic no longer holds valid values, so any output that is not correctly isolated spreads unknown values into the powered parts of the design and shows up as a failure.

Tests then exercise the power management sequence. The controller must assert isolation, save the state of retention registers, turn the supply switch off, and later reverse the steps in the right order. A wrong order, a missing isolation cell or a register that should have been retained shows up as corrupted data or a stuck design. Commercial tools add checks on top: Siemens describes static checks while reading the UPF and dynamic checks during simulation, and records power states and transitions as coverage so that the verification plan can track them.

The same checks are repeated after synthesis and physical design, because tools insert isolation cells, retention flip-flops and switches and update the power intent. Static low-power checkers complement simulation by checking structure without test vectors, but only simulation or emulation shows whether the sequence actually works.

Examples

• A test that switches a GPU domain off and on hundreds of times while checking that isolation holds its outputs at safe values.
• A retention test that saves a block's configuration registers, powers the block down, restores it and compares the state.
• Power states and transitions extracted from the UPF and tracked as coverage goals in the verification plan.
• A gate-level rerun with the post-synthesis netlist and updated UPF to confirm the inserted isolation cells behave as intended.

Why it matters

Power management bugs often lock a chip up or lose data only in particular power states, and they are hard to fix after tapeout. Low-power verification engineers, UPF power intent engineers and design verification teams run power-aware simulation, working with power architects who define the states and sequences.

Related terms

• UPF
• X-propagation
• Retention register
• Isolation cell

Where it appears on the Hub

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