Writing RTL that carries correct power intent: clock gating structures the tools recognize, isolation and level shifter placement, retention register selection, reset and handshake behaviour across power domains, all consistent with the UPF and verified by power-aware simulation.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: RTL design on a multi-domain SoC; grounded in IEEE 1801 UPF and in feedback from power-aware verification and signoff teams.
Register version 1.