Liberty

Notes

Originally a Synopsys format, donated to the industry and now maintained through the Liberty Technical Advisory Board.

Overview

Liberty is a text file format that describes how each cell in a library behaves for synthesis, timing and power analysis: its logic function, pin capacitances, delays, output transition times, timing constraints, power and noise data. A Liberty file normally covers one combination of process, voltage and temperature, so a library is delivered as a set of files, commonly with a .lib extension, one per corner. Synopsys maintains the format and licenses it openly through its TAP-in programme, and both commercial and open-source tools read it.

How it works

A Liberty file starts with library-wide settings such as units and operating conditions, then lists each cell with its area, pins and logic function, and for each output pin the timing arcs from the inputs that affect it. Delay and output transition for each arc are given as tables indexed by input transition time and output load, known as the non-linear delay model; tools interpolate between the grid points.

Beyond basic delays, Liberty can carry setup, hold, recovery, removal and minimum pulse width constraints, leakage and dynamic power, output current waveforms for more accurate delay calculation, noise propagation models and statistical data. The Liberty variation format (LVF) extension adds early and late sigma tables alongside the nominal values for on-chip variation analysis, and later versions add moments to describe skewed, non-Gaussian distributions.

The numbers come from characterisation. Each cell's extracted transistor netlist is simulated with SPICE models across a grid of input slews and output loads at each process, voltage and temperature corner, and the results are written into the Liberty tables. LVF data needs Monte Carlo simulation; Siemens EDA notes that characterisation tools use approximations to keep this to about five to ten times the runtime of nominal characterisation, at some cost in accuracy, so libraries need careful validation before release.

Examples

• Yosys mapping an RTL design onto the standard cells described in a Liberty file during open-source synthesis.
• An LVF library for a 5 nm process, where Siemens EDA notes that variation can change delays and constraints by up to 50 to 100 per cent of their nominal values.
• OpenSTA reading Liberty libraries with a Verilog netlist and SDC constraints to report the timing of a design.

Why it matters

Library characterisation engineers produce Liberty files, and synthesis, place-and-route, static timing and power engineers consume them every day. Memories, I/O cells and other hard IP are also delivered with Liberty models so that digital tools can treat them as black boxes with known timing and power. Errors in a library flow straight into every design that uses it.

In the chip lifecycle, Liberty files are created when a process and its foundation IP are developed, re-characterised when the foundry updates its device models, used from synthesis through place and route to timing and power signoff before tapeout, and compared against measured silicon during characterisation.

It matters most to: Library Characterization Engineer, Logic Synthesis Engineer, Memory Characterization Engineer, Standard Cell Library Engineer, Static Timing Analysis Engineer

Common confusions

Not the same as LEF

LEF describes a cell's physical abstract, such as its size, pins and blockages, for place and route. Liberty describes its electrical behaviour for synthesis and timing. Liberty vs LEF

Not the same as standard cell

A standard cell is the physical building block. A Liberty file is one of several views that describe it, alongside layout, abstracts and netlists.

Not the same as SPICE models

SPICE device models describe individual transistors and are used to characterise cells. Liberty summarises the result for whole cells, so digital tools never need to simulate transistors.

Sources

1. What is Library Characterization? (opens in a new tab), Synopsys, 2026-10-22
2. Technology Access Program (TAP-in) (opens in a new tab), Synopsys, 2026-10-22
3. Timing Library LVF Validation For Production Design Flows (WeiLii Tan, 27 February 2020) (opens in a new tab), Semiconductor Engineering, 2026-10-22
4. Yosys Open SYnthesis Suite (opens in a new tab), YosysHQ, 2026-10-22
5. OpenSTA (README) (opens in a new tab), Parallax Software, 2026-10-22
6. Public Standards and Solutions (opens in a new tab), Si2, 2026-10-22

Related terms

• NLDM
• CCS
• ECSM
• Characterisation
• Standard cell library
• Timing arc

Where it appears on the Hub

Used on 16 pages of the Hub. In each group, the pages that mention it most come first.