Also known as: Custom Digital Layout Engineer; Bitcell Layout Engineer; Full-Custom Layout Engineer; Custom Digital Layout Designer; Bitcell/Standard Cell Layout Engineer
See this role on the AMS lifecycle or on the PDK lifecycle or on the FPGA chip lifecycle
Builds the density-critical and rule-critical layouts that place-and-route tools cannot produce — standard cell libraries, SRAM bitcells and arrays, I/O cells, high-speed datapaths and memory compilers' leaf views.
Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction
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