Roles / Memory Compiler Engineer

Memory Compiler Engineer

PD-013v1

Physical Design & ImplementationImplementationIC4–IC7Individual contributor

Also known as: Embedded Memory Design Engineer; SRAM Compiler Engineer; Memory IP Engineer

See this role on the PDK lifecycle or on the Soft IP lifecycle

Summary

Builds and maintains the parameterised SRAM, register file, and ROM compilers that generate the embedded memory instances dominating SoC area and power.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Design bitcell periphery circuits including sense amplifiers, write drivers, decoders, and timing replica paths.
Develop compiler generators that produce layout, Liberty, LEF, and behavioural models across the configuration space.
Characterise memory instances for access time, setup/hold, standby leakage, and active energy per access across PVT.
Run statistical Monte Carlo analysis on bitcell read/write margin and sizing to meet the required sigma yield.
Implement assist techniques such as negative bitline, word-line underdrive, and read assist for low-voltage operation.
Integrate redundancy, repair, and BIST interfaces in coordination with the DFT and repair methodology teams.
Validate compiler output quality with automated DRC/LVS, Liberty QA, and functional regression over sampled configurations.
Support silicon characterisation of memory shmoo, Vmin distribution, and bitcell failure analysis.
Release compiler versions with documented configuration limits, datasheets, and integration guidelines.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Benchmark compiler area, power, and Vmin against foundry and third-party memory IP offerings.

Major tasks

Project

Produce and hand over the role's key deliverables
- Released memory compiler with full view set and datasheets
- Bitcell and periphery margin analysis with sigma yield assessment
- Characterisation corner matrix and Liberty QA evidence
- Redundancy and BIST integration specification
- Silicon Vmin and shmoo correlation report
Implement the layoutGeneral
- Floorplan and plan the power grid
- Place, build the clock tree and route
- Run extraction and analysis
Close sign-offGeneral
- Close timing at every corner
- Clear DRC and LVS
- Complete the sign-off checklist

Function

Maintain the flowGeneral
- Update scripts and flow settings
- Qualify new tool versions
Share knowledgeGeneral
- Document fixes for recurring issues
- Train newer engineers on the flow

Works with

Standard Cell Library Engineers
SoC Architects
Physical Design Engineers
DFT and Repair Engineers
Foundry Process Teams
Product Engineering

Typical backgrounds

MS/PhD in Electrical Engineering with memory or analog circuits focus; 5–15 years in embedded memory design.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

5 / 5

Remote feasibility

Medium

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Hsinchu, Santa Clara, Austin, Bangalore, Seoul, Boise, Shanghai, Yokohama

Certifications / standards training

—

Transfers to (industries)

Non-transferable outside semiconductor memory and IP design

Risk if vacant

SoC area, Vmin, and power targets are dictated by third-party memory IP, removing a primary lever for product differentiation and low-voltage operation.

Memory Compiler Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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