Roles / PDK Development Engineer

PDK Development Engineer

FAB-017v1

Process Technology & Fab OperationsImplementationIC3–IC6Individual contributor

Also known as: Process Design Kit Engineer; Design Enablement Engineer; PDK Release Engineer

See this role on the AMS lifecycle or on the Process node lifecycle or on the PDK lifecycle or on the Photonics lifecycle or on the Package technology lifecycle or on the SoC lifecycle

Summary

Packages the fab's process into a validated design kit — models, rules, decks and libraries — so external and internal designers can tape out manufacturable chips.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Lines tagged General are the Hub's general description of this kind of role, used where the role register has no entry yet. They are kept under review and will be refined.

Project

Work done for a product or program.

Build and release PDK components including SPICE model libraries, symbols, parameterised cells, techfiles and layer maps.
Develop and validate DRC, LVS, antenna, DFM and density rule decks for Calibre, Pegasus and IC Validator.
Codify design rules from process window data into a coherent, machine-checkable design rule manual.
Qualify PDKs across Cadence Virtuoso, Synopsys Custom Compiler and Siemens toolchains including version-matrix testing.
Run PDK regression suites and golden-testcase validation before each alpha, beta and production release.
Support parasitic extraction deck development and correlation for StarRC and Quantus QRC.
Manage PDK documentation, release notes, change logs and backward-compatibility policy.
Handle designer and customer PDK issues as the technical escalation owner, driving fixes into the next release.
Coordinate reliability, ESD and electromigration rule enablement with reliability and device teams.
Align PDK roadmap with technology milestones so design starts are never blocked by missing enablement.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Maintain implementation flows, scripts and sign-off checklists.General
Work with EDA vendors and the CAD team to fix tool issues and improve results.General
Feed lessons from each tapeout back into flows and guidelines.General

Major tasks

Project

Produce and hand over the role's key deliverables
- Versioned production PDK releases with release notes
- Design rule manual and rule deck set (DRC/LVS/DFM)
- PDK regression and qualification test reports
- Extraction deck and correlation package
- Customer-facing PDK documentation and issue log
Implement the layoutGeneral
- Floorplan and plan the power grid
- Place, build the clock tree and route
- Run extraction and analysis
Close sign-offGeneral
- Close timing at every corner
- Clear DRC and LVS
- Complete the sign-off checklist

Function

Maintain the flowGeneral
- Update scripts and flow settings
- Qualify new tool versions
Share knowledgeGeneral
- Document fixes for recurring issues
- Train newer engineers on the flow

Works with

SPICE modelling
device engineering
process integration
DTCO
foundry customers and internal design teams
EDA vendors
IP and standard cell library teams

Typical backgrounds

BS/MS in Electrical Engineering or Computer Engineering; 3–12 years in design enablement, physical verification or custom layout with process exposure.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

3 / 5

Remote feasibility

High

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Hsinchu, Taiwan; San Jose and Austin, USA; Bangalore and Hyderabad, India; Shanghai, China; Munich and Dresden, Germany; Singapore

Certifications / standards training

Cadence or Siemens EDA tool certifications; SEMI / iPDK-OpenAccess standards familiarity

Transfers to (industries)

EDA software development, photonic and MEMS design kit development, advanced packaging assembly design kits, IP provider enablement teams

Risk if vacant

Design starts stall or tape out against unvalidated rules, exposing the fab to silicon failures and customer escalations.

PDK Development Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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