StarRC

Notes

Extraction certification is node-specific, so upgrading StarRC mid-project usually requires a fresh foundry-approved ITF file.

Overview

StarRC is Synopsys's parasitic extraction tool, which calculates the unwanted resistance, capacitance and coupling of a chip's wires and devices from its layout so that timing, power and signal integrity can be analysed with realistic values. Synopsys positions it as a signoff extractor for digital, custom, analogue and mixed-signal, memory and 3D-IC designs. Its output feeds tools such as static timing analysis and circuit simulation, rather than giving answers on its own.

How it works

Every wire on a chip has resistance and capacitance to its neighbours and to the layers above and below, and the devices and contacts add more. Parasitic extraction computes these values so that a netlist can be annotated with them. Synopsys groups the parasitics by where they arise: in the devices themselves, in the contacts to the devices, and in the stack of interconnect layers.

There are two broad ways to compute them. A field solver solves the electromagnetic equations for the actual three-dimensional geometry; it is the most accurate method but too slow for a whole chip. A rule-based extractor instead looks up values in tables prepared in advance for the process, which is fast enough for full-chip runs. StarRC is used for full-chip extraction and includes its own field solver, Rapid3D, which can act as a reference or give higher accuracy on selected structures. Synopsys also sells separate reference solvers, QuickCap NX and Raphael.

Accuracy depends on the technology files supplied for each process, so extractors are qualified with foundries. In a 2020 announcement of a signoff flow for Samsung Foundry's 5 and 3 nm processes, Synopsys said StarRC extraction was within 1 per cent of the golden reference, with the StarRC field solver used as that reference. Synopsys also lists support for FinFET effects down to 3 nm and for 2.5D and 3D-IC extraction.

Examples

• Extracting a routed digital block and passing the parasitics to PrimeTime for static timing signoff.
• Extracting an analogue layout so that designers can rerun circuit simulation with real wiring loads.
• A foundry-qualified signoff flow for Samsung 5 and 3 nm processes that included StarRC extraction.
• Checking a critical clock net with the built-in field solver to confirm the rule-based values.

Why it matters

Timing, power and noise signoff are only as good as the parasitic values behind them, so extraction accuracy directly affects whether silicon meets its targets. Parasitic extraction engineers, timing signoff engineers and analogue designers running post-layout simulation depend on StarRC or a competing tool, and CAD teams keep its foundry technology files current.

Related terms

• PEX
• SPEF
• Quantus
• Synopsys
• PrimeTime

Where it appears on the Hub

Used on 5 pages of the Hub. In each group, the pages that mention it most come first.