725 abbreviations with 1,246 meanings, from the gate and discipline codes on the lifecycle charts to the standards, bodies and industry terms the Hub uses. Where the same letters mean different things, each meaning is listed with the lifecycles that use it. The list is built from the lifecycle and compliance data, so it stays current. For definitions of terms in general, see the glossary.
Measures the circuit on the bench across supply, temperature and process spread, explains the results against simulation and sets the trim and calibration values.
Discipline codes
In: AMS lifecycle
Speaks for the converter the device goes into: derives the mission profile and electrical requirements from traction inverters, onboard chargers, industrial drives, renewable energy and data-centre power supplies, estimates losses, builds evaluation boards and reference designs, sets gate drive guidance and supports customers through design-in.
Discipline codes
Turns the benchmark designs into reference designs, builds the development kits, writes the device documentation and supports lead customers through samples and family roll-out.
Discipline codes
A first kit with target device models, a draft design rule manual, basic decks and symbols goes to internal teams and selected partners for design studies and early IP work.
Gate codes
In: PDK lifecycle
Adoption across teams is reviewed against the business case, training records are complete, and the step moves to routine operation under monitoring.
Gate codes
The system, chip and software architectures are reviewed and approved, every risk control measure has a home in the architecture, the means of patient and operator protection are defined, the software safety class is confirmed, and the threat model and security architecture are agreed.
Gate codes
The assessment plan is agreed, the lead assessor is confirmed, and the project can show its real evidence for every process in scope.
Gate codes
Owns the architecture specification and the mitigation architecture: which functions are protected, by which mechanism, and how the part reports, corrects and recovers from radiation events, with the derating rules each block follows.
Discipline codes
In: Space lifecycle
Owns the product and system requirements and the architecture: redundancy, diagnostics, safe states, partitioning between chips, boards and software, and the traceability that ties them to the safety and security requirements.
Discipline codes
Turns product requirements into a chip architecture and a specification the design teams build from.
Discipline codes
In: SoC lifecycle
Turns the application into a link that closes: reach, data rate, wavelength plan, modulation, the link budget and the power and thermal envelope, then tracks the budget to measured silicon and systems.
Discipline codes
Designs the chip architecture with its safety mechanisms, decides how hardware and software share the safety work, and writes the specifications the design, verification and software teams build from.
Discipline codes
Defines the compute units, memory hierarchy, network on chip, chip-to-chip links and the interface software sees, within the power and thermal envelope, and keeps the microarchitecture consistent with them.
Discipline codes
Turns the idea into an architecture that can be built: the model that shows the advantage, the targets and the test chip's content, and checks them against test chip silicon.
Discipline codes
Defines the logic block, routing, memory and arithmetic blocks, clock network and input and output structure, judges them on benchmark designs with the software team, and keeps the device consistent with them.
Discipline codes
Defines the configurable cell, the split between fixed and custom layers, the routing, clock and power networks, the fixed blocks and the array sizes, and judges them by trial mapping of reference customer designs.
Discipline codes
Software that creates the test patterns a tester applies to find manufacturing faults in a chip.
Design and verification
Used in: Test program lifecycle: ATPG and pattern generation
Generates scan patterns for the agreed fault models with compression, memory BIST and logic BIST patterns, reports fault coverage, diagnoses scan failures on silicon and later trims and reorders patterns for test time.
Discipline codes
The first board revision's design is complete and its fabrication and assembly data go to the board manufacturer.
Gate codes
In: FPGA lifecycle
A kit with models fitted to silicon, most rules in place, validated decks, extraction and working PCells lets IP and library teams and early customers start real design work at an agreed risk.
Gate codes
In: PDK lifecycle
A versioned platform baseline is released for reuse: IP catalogue, software, firmware and SDK releases, reference designs, conformance tests and documentation.
Gate codes
Runs the source repositories, the reproducible build, continuous integration and the release process: tagging, packaging, release notes and the archive that lets any shipped version be rebuilt.
Discipline codes
Designs the board around the FPGA: schematics, layout, power supplies, high-speed channels and thermal design, often starting from a reference design.
Discipline codes
In: FPGA lifecycle
The business case is accepted and a team is funded to define the product.
Gate codes
In: Product lifecycle, SoC lifecycle, AMS lifecycle, FPGA lifecycle, Automotive lifecycle, AI accelerator lifecycle, Space lifecycle, Photonics lifecycle, Power and compound lifecycle, RF lifecycle, Medical lifecycle, Industrial lifecycle, System lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
The software scope that the chip's market needs is accepted as part of the product concept, and a software team is funded to define it.
Gate codes
A sensor opportunity is accepted and a team is funded to define what the sensor must measure, for which applications and at what cost.
Gate codes
The security the product's markets expect is accepted as part of the product concept, and a security owner is funded to define it.
Gate codes
The business approves development on the chosen concept, with a business case, a cost of ownership position against alternatives, and a development plan and budget.
Gate codes
The case for a shared platform rather than separate products is accepted, and a team is funded to define it.
Gate codes
Defines the item and its environment, turns the TARA into cybersecurity goals and claims, writes the cybersecurity concept and refines it into an architecture and component specifications.
Discipline codes
Tester results agree with the bench, with simulation and between testers and insertions, within agreed tolerances, so failures seen on the tester can be trusted as failures of the part.
Gate codes
The cell structure and array organisation are chosen, with evidence from simulation and early structures that they can reach the density and the cell behaviour the generation needs.
Gate codes
In: Memory lifecycle
Static, dynamic and ruggedness behaviour is measured across temperature, compared with the design and the target datasheet, and the differences are explained.
Gate codes
Facility systems are commissioned and the cleanroom is certified to its cleanliness class, so tools can be moved in and connected.
Gate codes
The assessment report is issued, the capability profile is compared with the target, and the sponsor and customer agree what follows.
Gate codes
Cybersecurity goals and claims are agreed and the cybersecurity concept allocates requirements to the architecture, the operational environment and suppliers, without unresolved conflicts with safety.
Gate codes
Runs the change process after approval: classification, impact assessment across FMEAs, control plan and approvals, customer notification, requalification tracking, and the end of production and record retention.
Discipline codes
In: APQP lifecycle
The hardware architecture, device technology, component set and software architecture are reviewed and accepted, and the preliminary system safety assessment is updated with the design's fault tolerance and independence.
Gate codes
Designs custom silicon for the device, such as biopotential and sensor analog front ends, stimulation and drive circuits, ultra-low-power processing and power management, with chip-level risk controls, reliability and supply life built into the specification and the design.
Discipline codes
Designs the controllers, isolators, gate drivers, sensor interfaces and power management chips with built-in diagnostics, monitors, redundant channels and secure elements, and supports their analysis and test.
Discipline codes
Engages early customers and ecosystem partners, certifies tool flows, runs multi-project wafer shuttles and supports customer designs through tape-out and their own product qualification.
Discipline codes
The certificates or assessment results the plan requires are issued, with any conditions recorded.
Gate codes
Certificates, listings and declarations of conformity are issued for every target market, and the technical file is complete, so the product can be placed on those markets.
Gate codes
The second stage audit is complete, nonconformities are answered and accepted within the time the scheme allows, and the certification body has issued the certificate.
Gate codes
In: QMS lifecycle
Brings customers' workloads into the plan, runs early access, ports and qualifies customer models, writes porting guides and handles field issues for the life of the product.
Discipline codes
Gets customers productive and keeps them so: early-access and beta programs, developer documentation, porting guides, training, issue intake from the field and the migration path at the end of support.
Discipline codes
Assesses each customer design for fit, converts FPGA prototypes to the base array, reviews the design with the customer and supports them until they approve the samples.
Discipline codes
Characterises the libraries for timing, power and noise at the agreed corners on each model release, generates and checks their views, and runs library QA before each library release.
Discipline codes
In: PDK lifecycle
Plans and runs characterisation across corner lots, voltage and temperature, sets test limits and guard bands from the data, and later supplies the data that justifies removing or sampling tests.
Discipline codes
Measures the devices: static characteristics, capacitances and gate charge, double pulse switching, body diode and reverse recovery, avalanche and short-circuit ruggedness, threshold stability and dynamic on-resistance for gallium nitride, across temperature, and repeats the comparison for larger wafers and in the target circuit.
Discipline codes
Plans the measurements, designs evaluation boards and fixtures, calibrates the bench, measures S-parameters, noise, linearity, power and spectral performance with de-embedding, and writes the characterisation report and datasheet values.
Discipline codes
In: RF lifecycle
Finds lead customers, turns their product needs into shared requirements, runs the joint development agreement and its reviews, supports customer designs and sample builds, and secures the customer's approval for volume.
Discipline codes
The calibration model, procedure and stimulus equipment are approved, and calibrated parts meet the accuracy targets across temperature with the residuals understood.
Gate codes
The organisation's cybersecurity management system is in place, audited and able to support projects; for a vehicle maker it is ready for, or holds, a certificate of compliance under UN R155.
Gate codes
Owns the configuration management plans, baselines, problem reporting, change control, the environment and configuration indexes and the archive, so that any delivered item can be traced to, and rebuilt from, its data.
Discipline codes
Identifies configuration items, controls their versions, branches and baselines, records and tracks every problem to closure, and runs change requests through analysis, approval, implementation and confirmation.
Discipline codes
Keeps the platform baselines, versions and change control, assembles each platform release, audits derivatives against it, and archives the platform at its end.
Discipline codes
Allocates banked wafers to each customer design, orders its custom masks, finishes and packages its wafers, and plans the bank and capacity for the device through to the last builds.
Discipline codes
Works out which approvals each market needs, plans them from the start, runs pre-compliance and formal tests with accredited laboratories, and holds the certificates and declarations of conformity.
Discipline codes
In: System lifecycle
Owns the business case, the cost model across dies, package, assembly and test, the relationship with any third-party chiplet suppliers, and the plan with lead customers through sampling to production release.
Discipline codes
Lead customers have qualified the part in their own products, by their own tests or a production part approval where their market asks for one, and approve it for their production, or have agreed when they will.
Gate codes
The die, package and stack pass their qualification to the published JEDEC methods and the target application, and the result is recorded.
Gate codes
In: Memory lifecycle
A cost or improvement change, such as a die shrink, a new material source or an assembly change, has been qualified and notified to customers, and is ready to implement.
Gate codes
At least one lead customer product built on the technology passes the customer's qualification and system evaluation, and the customer approves it for volume.
Gate codes
Owns the relationship with the customer's quality organisation: captures the voice of the customer and every customer specific requirement, prepares and submits the PPAP, handles customer portals, scorecards, complaints and change notifications.
Discipline codes
Samples of the revision that carries the fixes from lead customer feedback are released to the wider customer base, with an updated datasheet, the current errata and the evaluation kit, so more customers can evaluate and design in the part before it is qualified.
Gate codes
Characterised parts with a preliminary datasheet and known limits go to lead customers for evaluation.
Gate codes
The device architecture and the main module options are chosen, with evidence from simulation and short experiments that they can work together.
Gate codes
The transduction principle, the structure and the process route are chosen together, with multiphysics evidence that the concept can meet the error budget.
Gate codes
One package structure is chosen from the options studied, with modelling evidence that it can meet the electrical, thermal, mechanical and cost targets, and the remaining gaps are named.
Gate codes
Timing, physical checks, test coverage and equivalence are clean on the design placed and routed on the fixed base, and the customer has signed off the final design.
Gate codes
Answers customer questions and escalations after launch, keeps the support knowledge base and order fulfilment working, and carries the support and warranty obligations past the last shipment.
Discipline codes
Gives customers what they need to use the product securely: the secure integration guide, provisioning and key handling support, security notices and migration guidance at the end of support.
Discipline codes
Builds security into the device under IEC 81001-5-1 and the security expectations of the target markets: threat modelling, security architecture, secure boot and update, security testing, the security risk report, vulnerability monitoring and coordinated disclosure.
Discipline codes
Owns the electronic component management plan, component selection and qualification, counterfeit parts avoidance to AS5553 and AS6081, supplier control, export classification and the obsolescence plan through to the last-time buy.
Discipline codes
Where the cybersecurity plug-in is in scope, derives cybersecurity requirements from the threat analysis and risk assessment, designs them into the architecture, implements and verifies them, and keeps cybersecurity risk management and supplier cybersecurity in step with the engineering processes.
Discipline codes
Chooses the chips, FPGAs and modules the system uses, writes the requirements for any custom chip and follows it through its own lifecycle, and brings the suppliers' design-in material and errata into the system design.
Discipline codes
In: System lifecycle
Finds out what customers actually need, recruits design partners, supports their evaluations and turns their results into product requirements, purchase orders and a pipeline of design wins.
Discipline codes
The design database, verification and test data, the production test program and the qualification records are archived, so later questions from customers or the field can still be answered.
Gate codes
In: SoC lifecycle
The design team and the test team agree the test features the chip carries and how each one will be used on the tester, so the design can be built to be testable at the cost the plan allows.
Gate codes
Security, legal and the business owner approve the data flows, storage, retention, training rights, output ownership, licence terms and export position for production use, and the supplier agreement reflects them.
Gate codes
The functions, failure conditions and their classifications are agreed with the system integrator, and every hardware and software item has a development assurance level with its rationale.
Gate codes
The cybersecurity architecture and component specifications are complete and verified against the concept, and supplier requirements are flowed down.
Gate codes
A new product derived from the platform is approved: its market, its configuration of the platform, what it adds and its business case.
Gate codes
Designs how debug and test access is authenticated and locked across the device lifecycle states, so scan, test modes and debug ports cannot be used to reach secrets in the field.
Discipline codes
All planned logic is written, integrated and reviewed.
Gate codes
In: FPGA lifecycle
When a fab or area closes, tools are removed or transferred, systems are decontaminated, the site is remediated and permits and agreements are closed.
Gate codes
The business commits the investment in MEMS process, ASIC, package, calibration and qualification, against an agreed development plan, cost target and reliability requirements.
Gate codes
The derivative's configuration and new content are verified against the platform rules: the conformance tests pass, and every deviation from the platform is recorded and approved.
Gate codes
Controls documents and records: approval, versions, distribution, access, retention and disposal, the quality manual or system description, and the change management that keeps documents in step with processes.
Discipline codes
In: QMS lifecycle
Structures added to a chip, such as scan chains and built-in self test, so it can be tested after manufacture.
Design and verification
Used in: SoC lifecycle: Full-Chip DFT, SoC lifecycle: DFT insertion sign-off gate, Soft IP lifecycle: IP DFT & Implementation Views, Automotive lifecycle: DFT and in-system test, Test program lifecycle: Test Strategy & DFT Alignment, Test program lifecycle: DFT architecture aligned gate, and 5 more
Adds and connects the full-chip test structures, such as scan chains and built-in self-test, around each IP block's own, so every manufactured chip can be tested.
Discipline codes
In: SoC lifecycle
Designs test access for production test and for in-system tests the chip runs in the vehicle, such as logic and memory built-in self-test at start-up and during operation, and generates the test patterns.
Discipline codes
Agrees with the chip design team the test features the chip carries (scan, compression, memory BIST, logic BIST, boundary scan, IEEE 1500 wrappers and IEEE 1687 instruments) and describes how the tester reaches each one.
Discipline codes
Every engineering lifecycle in the product has signed off its part and released it for manufacture, such as a SoC tape-out, an analog block hand-off or an FPGA bitstream with its board, and the business is ready to build, validate and sample.
Gate codes
Schematic-level design is complete with electromagnetic models of every critical passive in the simulation, and the circuits meet their block specifications across corners before layout is committed.
Gate codes
In: RF lifecycle
The security blocks and the boot and security code are implemented, and an independent secure design review has found no open high-severity issue.
Gate codes
The detailed hardware design and the software low-level requirements and source code are complete for the baseline, reviewed against their standards, traced, and ready for implementation; the design review with the certification authority, where held, has its findings recorded.
Gate codes
Every process of the system is defined with an owner and measures, and the documented information is released under control so implementation can be measured against it.
Gate codes
In: QMS lifecycle
The derivative product is released for production through its own chip and product lifecycles, on a named platform version.
Gate codes
The device configures from each supported source, encrypted and authenticated bitstreams load, the bring-up designs run with correct results, every hard IP block has been brought up, and differences from the design are listed as errata.
Gate codes
Writes the operating system drivers for the chip's blocks and the board support package that brings an operating system up on the reference boards, and carries them across new operating system versions.
Discipline codes
Every coded rule in the design rule check, layout versus schematic, antenna, density and electrical rule decks has been run on layouts written to pass and to fail it, in each supported tool category.
Gate codes
In: PDK lifecycle
Units built close to production pass functional, performance, power, thermal, environmental, reliability, software and security testing against the requirements, with any differences recorded and dispositioned.
Gate codes
In: System lifecycle
The first parts have been tested against the customer device specification across voltage and temperature, with any differences listed.
Gate codes
Proves the full chip does what the specification says, through simulation, emulation, formal methods and coverage, relying on each IP block's own verification.
Discipline codes
In: SoC lifecycle
Plans and runs simulation, formal checks and performance verification, and builds the emulation platform on which the software stack runs real workloads before tape-out.
Discipline codes
Writes and verifies the RTL for the test chip's reduced scope, builds the verification environment the product reuses, and roots out the cause of issues found on test chip silicon.
Discipline codes
Verifies the fabric, the configuration logic, the security features and the hard IP connections, including simulation of the device model programmed with bitstreams from the vendor's own software.
Discipline codes
Verifies the base array, its cells and fixed blocks, and test designs through the reference flow, and builds the environment that each customer design reuses.
Discipline codes
Extracted resistance and capacitance agree with measurements on interconnect test structures within the accuracy targets set in the plan, and the electromigration rules are drafted.
Gate codes
In: PDK lifecycle
The part and its technology have a first export classification, and a technology control plan says who may see the design data and where it may go.
Gate codes
In: Space lifecycle
Before any tool, part, software or technical data leaves for a customer, the tool and its technology are classified under the export rules that apply and any licences needed for the first shipments are held.
Gate codes
Designs the tool's electrical systems: power distribution, RF and high-voltage supplies, motion and robot control hardware, sensors and input and output, safety circuits and interlocks, cabling and electrical drawings.
Discipline codes
The software tools used to design, simulate, verify and lay out chips.
Design and verification
Used in: Tool and flow decisions, PDK lifecycle: EDA tool and reference flow enablement, Startup lifecycle: EDA, compute and design infrastructure
Agrees which tool categories and versions the kit supports, ports decks and technology files to each, and certifies the reference design flows customers use on the node.
Discipline codes
In: PDK lifecycle
The product's discontinuance is announced and the test plan for the last-time buy is agreed: capacity, hardware spares and the final test runs.
Gate codes
The candidates to evaluate, the reference designs with known answers and the success criteria are fixed before any result is seen, so the pilot cannot be judged on what it happened to do well.
Gate codes
Series supply of the part has ended as notified: last-time-buy orders are shipped, any service supply is in place, and records are retained for the agreed period.
Gate codes
In: APQP lifecycle
Runs the design at speed on emulators and FPGA prototypes before the final hardware exists, so firmware and software can be brought up and hardware and software verified together.
Discipline codes
Works with equipment and materials suppliers so that each new tool, chemical, gas and substrate is ready, qualified and in supply when the node needs it, and stays in supply to the end of its life.
Discipline codes
Validated early parts go to lead customers for evaluation and design-in, with known issues documented and the agreements and export checks for sample shipments in place.
Gate codes
In: Product lifecycle, SoC lifecycle, Chiplet lifecycle, Automotive lifecycle, Memory lifecycle, Photonics lifecycle, Power and compound lifecycle, MEMS and sensors lifecycle, RF lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
Builds from last-time-buy stock have ended, the final field update and security advisory are published, and repairs and support end as announced, with the design, bitstream sources and build environment archived.
Gate codes
In: FPGA lifecycle, Medical lifecycle, Avionics lifecycle, Industrial lifecycle, System lifecycle
The final release and final security advisory have shipped, the source, build environments and signing records are archived, and support closes.
Gate codes
The final lots are built, screened and shipped, and every record the missions may need is archived.
Gate codes
In: Space lifecycle
The security target and the evaluation evidence package are complete and handed to the evaluation laboratory or assessor.
Gate codes
Maintenance and security releases for the platform end as announced, and its IP, software, tools and records are archived.
Gate codes
Helps derivative teams and customers use the platform: documentation, training, support handovers, usage metrics and migration guidance when the platform retires.
Discipline codes
Classifies the part and its technical data under the export rules that apply, such as ITAR or the EAR with its ECCN, writes and runs the technology control plan, obtains licences or other authorisations, screens every party and destination, and keeps the records the rules require.
Discipline codes
In: Space lifecycle
An engineer who helps customers design a company's chips into their products.
Business and product lifecycle
The technical bridge to customers: brings their use cases into the definition, builds evaluation kits, reference designs and application notes, supports design-in, and helps customers migrate at end of life.
Discipline codes
Supports customers who integrate the product into safety systems, machinery and plants, collects field failures and returns, and feeds field data back into the FMEDA, the safety case and the next design.
Discipline codes
Handles customer returns and field failure analysis, runs the product change notification process, monitors safety-relevant field issues, and plans for obsolescence and end of supply.
Discipline codes
Analyses customer returns and field failures, leads problem solving with 8D or an equivalent method, feeds causes back into the FMEAs and control plans, and keeps the lessons learned database.
Discipline codes
In: APQP lifecycle
The first wafers or packaged parts from the design release are back and pass their first power-up and basic tests, so bring-up and validation can start and the business can confirm or reset the sample dates it has given customers.
Gate codes
In: Product lifecycle, SoC lifecycle, AI accelerator lifecycle, Memory lifecycle, Space lifecycle, RF lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
Packaged test chips are back, power up and respond on the test boards, so measurement and reliability testing can start.
Gate codes
First wafers or packaged parts arrive and start testing, with the debug team, the tester time and the bench equipment ready.
Gate codes
Packaged product silicon has arrived and powers up on the evaluation board, and the bring-up team has started working through the silicon validation plan.
Gate codes
Gets tools installed and keeps them running: installation and site preparation procedures, start-up and acceptance tests, maintenance procedures and training, service delivery and escalation, spare parts planning and the register of every installed tool and its configuration.
Discipline codes
Plans and runs the functional safety lifecycle: roles, competence, independence, configuration and change control, the safety case, confirmation measures and the functional safety assessment.
Discipline codes
Supports customers once the system ships: service and repair, field issues and returns, field quality reporting, spares and the support commitments until the end of support.
Discipline codes
In: System lifecycle
Tests the assembled unit through its die-to-die links, applies lane repair, and runs burn-in and system-level test, releasing the final test program with the package qualification.
Discipline codes
The first device wafers are out of the fab on the frozen baseline, with wafer-level test data, and the characterisation plan and equipment are ready.
Gate codes
The first MEMS wafers and interface ASIC wafers are out, probed and ready to be built into prototype assemblies.
Gate codes
Writes the boot code, drivers and reference software that run on the chip.
Discipline codes
In: SoC lifecycle
Writes the firmware that runs on the chip's own controllers, such as power management, system control and security cores, often on a real-time operating system or bare metal, and the boot loaders that carry the chain of trust from the boot ROM to the operating system, and keeps them updated in the field.
Discipline codes
Designs the secure boot chain and writes the boot ROM security code, security firmware and cryptographic libraries, then writes the fixes that security updates deliver.
Discipline codes
Writes the boot code, firmware and board support the system runs on, first on the virtual prototype and the emulation and FPGA prototypes, then on the real boards, and keeps updating it in the field.
Discipline codes
In: System lifecycle
Writes the boot code, firmware and board support shared by the platform's products, first on the virtual platform and prototypes, then on the lead product's silicon, and maintains them for every derivative.
Discipline codes
Owns the macro's business case, its integrators and licensees, the process ports on the roadmap, the releases and the end of support.
Discipline codes
Designs the boards, power supplies, isolation barriers, patient connections and enclosure electronics, places the means of patient and operator protection, and runs hardware bench tests before type testing.
Discipline codes
Owns the hardware design plan, the hardware requirements, the conceptual and detailed design of programmable devices, ASICs and boards, and the hardware build, following DO-254 at the assigned level.
Discipline codes
Designs the boards, power stages and isolation barriers to the safety concept and the insulation concept, with EMC-aware layout and components approved for the temperature, life and supply needed.
Discipline codes
Where hardware engineering is in scope, derives hardware requirements, designs the hardware and its interfaces to software, verifies the design and the built hardware against its requirements, and keeps it traceable to the system level.
Discipline codes
Specifies and verifies the hardware security functions the item relies on, such as a hardware security module, secure boot, key storage, cryptographic acceleration and debug protection, and provides chip-level evidence and a security manual to integrators.
Discipline codes
Every customer and supplier relationship that shares cybersecurity work has an agreed interface agreement saying who does what, which work products are exchanged, and how vulnerabilities and incidents are reported.
Gate codes
Plans and runs the audit programme with qualified auditors: system audits against the standards, process audits, product audits and the follow-up of findings, and checks that layered process audits are effective.
Discipline codes
In: QMS lifecycle
Defines what the block does, its interfaces and the configuration options an integrator can choose, and supports the specification until the block is verified.
Discipline codes
Proves the block meets its specification in each supported configuration, and often supplies verification IP the SoC team reuses.
Discipline codes
Prepares and runs incident response: the plan and its rehearsals, triage, containment, root cause analysis with suppliers, remediation, communication with customers, authorities and partners, and lessons learned.
Discipline codes
Plans and runs the prototype builds, brings boards, chips, firmware and software up together in the lab, and keeps the integration issue list until the design is frozen.
Discipline codes
In: System lifecycle
Chooses each IP block, takes its release from the IP lifecycle or a supplier, and connects it into the SoC.
Discipline codes
In: SoC lifecycle
Writes the technology definition, joins the modules into one flow, tunes the devices, freezes the baseline and owns the integrated process through qualification.
Discipline codes
A reusable, licensable design block, such as a processor core or an interface, that is integrated into a chip.
Design and verification
Used in: Soft IP lifecycle, SoC lifecycle: IP Integration, SoC lifecycle: IP integration complete gate, SoC lifecycle: IP integration, Soft IP lifecycle: IP Specification & Architecture, Soft IP lifecycle: IP Verification, and 48 more
The repaired or new standard processes are reviewed, and the improvement plan with its owners, resources and timetable is approved.
Gate codes
Decides which blocks to license rather than design for the test chip, evaluates and negotiates for them, integrates them and supports them on test chip silicon.
Discipline codes
Designs and verifies the platform's IP blocks and subsystems to a reuse standard, configures them for each derivative and keeps them maintained for every product that uses them.
Discipline codes
Owns the block's roadmap, the SoC teams and customers that use it, and its releases and support.
Discipline codes
A versioned release package goes to the SoC teams, with its documentation and a route for support.
Gate codes
Each incident is closed with its cause understood, remediation delivered and lessons applied to the item, the process and the next projects.
Gate codes
Runs the product security incident response team: the public reporting channel, triage and severity rating, coordination of fixes, coordinated disclosure, CVE identifiers and security advisories until the end of support.
Discipline codes
Evaluates blocks from suppliers, agrees the licence, checks each delivery from the supplier and accepts the final one before it goes to SoC teams.
Discipline codes
Sets the laser requirements, chooses and qualifies how the laser is integrated, and secures laser supply for production.
Discipline codes
Forms the company and protects what it owns: founder and employee agreements, IP assignment, patents, confidentiality, the foundry, EDA, IP and design partner agreements, export classification and the first customer supply agreement.
Discipline codes
Agrees the evaluation terms, reviews licence, confidentiality, training rights and output ownership for production use, assesses export control, writes disclosure guidance and reviews every change of terms.
Discipline codes
Chooses and develops the patterning approach for each layer, builds the optical proximity correction models, and prepares the mask sets for test vehicles.
Discipline codes
The compact models are fitted to measurements from the frozen process baseline, with the remaining gaps to target stated, so the next kit can support real design work.
Gate codes
In: PDK lifecycle
Qualifies suppliers and critical components, including the foundry and assembly partners for custom chips, builds pilot units, writes production test specifications, validates processes and releases production with unique device identification and traceability.
Discipline codes
Scales production, improves yield and keeps the supply running.
Discipline codes
In: SoC lifecycle
Introduces the product to manufacturing, programs and tests each unit, and manages component supply, including the FPGA device's own end-of-life notices.
Discipline codes
In: FPGA lifecycle
Models the cost of ownership, plans capacity, readies the fab for risk and volume production, transfers the process to further fabs where needed, and runs the final wafer starts.
Discipline codes
Plans and runs wafer starts, test and assembly capacity, die bank and inventory across grades, the ramp and the final builds, and delivers committed allocations.
Discipline codes
In: Memory lifecycle
Prepares and runs the fab as a factory: operations readiness, shift structure, wafer start and dispatch plans, maintenance, spares, cycle time and output, the factory performance report and continuous improvement, and the wind-down and customer transfers at the end.
Discipline codes
Plans the MEMS fab, ASIC foundry, assembly and test supply chain, orders prototype and production wafers, ramps capacity with calibration equipment included, tracks unit cost and runs the last-time-buy builds.
Discipline codes
Runs the pilot line and then volume manufacturing: lot starts, work instructions, inline inspection and process control, yield learning and defect reduction, cycle time, and the final builds at end of life.
Discipline codes
Assesses the process and package technology, places the mask and wafer orders, builds the first packaged parts, and plans capacity and long-term supply through to the last builds.
Discipline codes
Agrees wafer banking with the foundry, plans the bank, and builds, accepts and holds the base wafers that every customer design is finished on.
Discipline codes
Collects cybersecurity information from the field and from suppliers, researchers and public sources, evaluates events, analyses and manages vulnerabilities, reports monitoring results and announces the end of cybersecurity support.
Discipline codes
Develops and sustains the unit processes, such as etch, deposition, implant, thermal steps, planarisation and cleans, to their capability targets on the chosen tools.
Discipline codes
Builds and releases the SPICE compact models: target models first, then models fitted to baseline silicon, process corners, statistical and mismatch models, and final models correlated to production silicon.
Discipline codes
In: PDK lifecycle
Builds the models customers and internal teams simulate with: compact SPICE models of the device including temperature and body diode behaviour, thermal network models of packages and modules, and the loss data behind online calculators, fitted to silicon and released with stated limits.
Discipline codes
Designs the module or antenna-in-package: substrate, filters and passives, die-to-package-to-board transitions, antennas and arrays, thermal paths, and builds and measures the module samples.
Discipline codes
In: RF lifecycle
The package or power module, with its die attach, interconnect and substrate, has passed its own qualification, such as power cycling and thermal cycling, and its assembly process is frozen.
Gate codes
Plans manufacturing test of die, memory stacks and package, runs reliability qualification of the chip and the system, releases production and system-level test, and keeps quality and supply in control through to the final build.
Discipline codes
Builds the prototypes and type test samples, releases the production test program with the routine safety tests, owns the production control plan and traceability, and hosts factory inspections.
Discipline codes
Assembled modules are measured as the customer will use them, including antenna patterns and beam steering for arrays, and are ready for pre-compliance testing and customer evaluation.
Gate codes
In: RF lifecycle
The substrate or interposer technology and the key materials are chosen with measured properties, supplier commitments for development quantities and a first view of volume supply.
Gate codes
Prepares and runs the building of tools: make or buy, should-cost, critical suppliers and their qualification, the released bill of materials, build instructions, supply plans, build quality and cycle time, standard cost and last-time buys of parts.
Discipline codes
Makes sure every gauge, metrology tool and tester that checks a characteristic in the control plan is capable: calibration, gauge studies, tester to tester correlation and guard band setting.
Discipline codes
In: APQP lifecycle
Prepares the system for volume: design for manufacture, suppliers and the approved vendor list, the validation and production builds, production test, the production bill of materials, the ramp and last-time buys.
Discipline codes
In: System lifecycle
Selects and develops the substrate or interposer technology, dielectrics, underfills, mould compounds, thermal interface materials, solders and bonding layers with their suppliers, measures their properties and qualifies them.
Discipline codes
Selects the ATE platform and test sites, transfers the program to production testers at the internal floor or a test subcontractor, proves capability, and runs the test floor through the ramp and end of life.
Discipline codes
Chooses the foundry and process for the test chip, books the shuttle, delivers the database for the run and tracks the test chips back to the lab with their cost and schedule actuals.
Discipline codes
Plans wafer, substrate, filter, assembly and test supply, readies the ramp, runs change notification with customers, and manages the last-time buy and the archive.
Discipline codes
In: RF lifecycle
A company that packages and tests chips for others.
Manufacturing, test and packaging
Selects and manages the outsourced assembly and test suppliers and the supply of wafers and substrates, gets their lines ready and plans their capacity.
Discipline codes
Product requirements, cost and price targets, schedule, make, buy or partner choices and resources are agreed, and the business commits the funding for full development.
Gate codes
A future node is put on the technology roadmap and a pathfinding team is funded to explore how it could be built.
Gate codes
The conditions for a bounded pilot are in place: what data may be used and where it may go, an evaluation agreement with the supplier, and the budget, people and isolated environment the pilot needs.
Gate codes
The integrated prototype passes its internal acceptance tests in the demonstration lab: functions, process results on test wafers, safety and early reliability.
Gate codes
Production is approved by the authority or accepted by the integrator, the obsolescence management plan is active and delivery of conforming units has started.
Gate codes
The customer has nominated the part or the business has approved a new automotive part, and a cross-functional APQP team is named with a leader, a schedule tied to the customer's program milestones and a list of the customer specific requirements that apply.
Gate codes
In: APQP lifecycle
Cost, schedule, resources and feature set are agreed between the business and engineering, and development of the system is committed.
Gate codes
In: System lifecycle
Owns the product assurance plan, the compliance evidence against QML or ECSS requirements, the parts, materials and processes list, the quality level and procurement specification, design reviews, nonconformance and the material review board, and the release of every flight lot.
Discipline codes
In: Space lifecycle
Develops and proves the process results the tool exists to deliver: process requirements with customers, feasibility on test hardware, recipes, process windows, matching between tools and the process data customers qualify on.
Discipline codes
Owns the hardware process assurance plan and the software quality assurance plan, audits that plans and standards are followed, transition criteria checks, conformity reviews and the quality system that production runs under.
Discipline codes
Defines what every product on the platform shares and where products may differ: the reference architecture, the variation points, the platform interfaces and the rules a derivative must follow.
Discipline codes
Writes the product specification from the test chip's silicon evidence, the design partners' needs and the product requirements, and supports it through to product tape-out.
Discipline codes
Owns the sensor's business case, target applications, cost and pricing, sampling and customer commitments, and decides when to change, derive or withdraw it.
Discipline codes
Every pattern set the program needs exists in the tester's format and has passed simulation against the final netlist with tester timing, with the fault coverage it achieves recorded against the goal.
Gate codes
The pilot ran as planned, every output was checked against the known answer, and the results, failures and user feedback are reviewed to decide whether formal qualification is worth doing.
Gate codes
The construction and start-up project is closed: spend reconciled, as-built records handed over, incentive milestones reported, lessons recorded and the fab handed to operations.
Gate codes
In-house scans show margin to the regulatory limits and the standard's conformance requirements, so formal testing at an accredited laboratory can be booked with confidence.
Gate codes
In: RF lifecycle
Owns the business case, the customer requirements, the program plan, the certification plans and the liaison with the certification authority and the integrator, through the accomplishment summaries to in-service support and end of support.
Discipline codes
Plans the standards, schemes and markets, works with test laboratories, certification and notified bodies, and keeps certificates, declarations, the technical file and factory inspections current.
Discipline codes
Runs production to the control plans: statistical process control on special characteristics, reaction plans, layered process audits by every level of management, contingency plans and the total productive maintenance that keeps equipment capable.
Discipline codes
In: QMS lifecycle
What the platform shares and where products may differ are agreed: the products it serves, the common core, the planned variation points and what each derivative is expected to reuse.
Gate codes
Turns the full-chip netlist, with each IP block's physical views, into a manufacturable layout and closes timing, power and physical checks.
Discipline codes
In: SoC lifecycle
Implements the design for the mission profile and temperature grade, signs off electromigration, ageing and timing at the automotive corners, and keeps redundant logic physically apart where the safety analysis needs it.
Discipline codes
Floorplans and implements a large, power-dense die, plans the package with its high-bandwidth memory, closes timing and power integrity, and releases the database and package design to manufacture.
Discipline codes
Turns the test chip RTL into a database the shuttle accepts: flow and design kit trials, synthesis, test insertion, place and route, timing and physical sign-off, then correlation with silicon.
Discipline codes
Implements the layout with radiation rules, such as separation of redundant elements and latch-up structures, and signs off timing, power and reliability at the corners the dose budget sets.
Discipline codes
In: Space lifecycle
Assembles the full device layout from tiles, hard IP, clock and power networks and the input and output ring, closes timing and the physical checks, and tapes out each family member.
Discipline codes
The set of device models, rules, decks and libraries a foundry gives designers so their design can be built on its process.
Design and verification
Used in: PDK lifecycle, Process node lifecycle: PDK & Design Enablement Development, Process node lifecycle: Early access PDK release gate, Process node lifecycle: Design-start PDK release gate, Process node lifecycle: Pre-production PDK release gate, Process node lifecycle: Production PDK release gate, and 14 more
Builds and releases the process design kit in versions of rising maturity: models, design rule manual, verification and extraction decks and technology files, each release checked before it goes out.
Discipline codes
Brings the foundry's photonic design kit and the component library into the flow, fits and refreshes compact models from measured data, and keeps the verification decks the layout is checked with.
Discipline codes
Writes the assembly and substrate design rules, assembles the package design kit with stack-ups, models, libraries, checking decks and reference designs, releases it in versions and supports customers who design with it.
Discipline codes
Plans and coordinates the development programme across hardware, software, process, supply and customers: the charter, plan and budget, the risk register, evaluation schedules, gate reviews, production readiness and the programme's lessons learned.
Discipline codes
Runs the cross-functional plan: the schedule, the dependencies between the engineering lifecycles and the business functions, the risk and issue lists, the gate reviews and their records.
Discipline codes
Owns the kit's scope, plan and releases: what each release must contain and how mature it must be, the release decision at each gate, and the kit's life to its end.
Discipline codes
In: PDK lifecycle
Owns the business case, the product plan and the gates: which application and customers the product serves, what it must cost, when it ships and when it is withdrawn.
Discipline codes
Runs the fab build as one programme: the master schedule, cost control, risk register, contracting strategy, interfaces between contractors, suppliers and the owner's teams, reporting, and the formal close-out and handover.
Discipline codes
Takes in each customer's requirements and FPGA prototype, quotes the design from the feasibility report and the platform's pricing model, agrees the statement of work, runs the customer programme through sign-off and samples, and keeps deliveries in step with the customer's demand.
Discipline codes
A project starts on the released processes, with its tailoring approved by the process owner.
Gate codes
Selects and designs the package, often hermetic ceramic or a qualified non-hermetic alternative, owns the assembly drawings and materials, and qualifies the package to the agreed framework.
Discipline codes
In: Space lifecycle
Owns the product from concept to end of support: the product requirements, the roadmap fit, the business case after approval, the trade-offs between scope, cost and schedule, and every lifecycle decision.
Discipline codes
In: Product lifecycle, SoC lifecycle, FPGA lifecycle, System lifecycle
Owns the business case, the customer requirements, the development interface agreement with each customer, the mission profile and the long-term supply commitment.
Discipline codes
Owns the business case, the product requirements across silicon, system and software, the plan and the schedule, the early access and launch, the software roadmap after launch and the end of support.
Discipline codes
Owns what the software stack is for: the software requirements, roadmap, supported platforms, support period and release approvals, balancing customer needs against cost.
Discipline codes
Plans the adoption across projects, keeps the roadmap of AI-assisted steps, runs the first project plan and the transition when a step is retired, and reports adoption status.
Discipline codes
Owns the tool as a product: the customers' process roadmaps it serves, the market and competitive view, the business case including service and upgrades, pricing and configurations, the choice of evaluation customers, and the platform's lifecycle decisions.
Discipline codes
Owns the business case, the device concept, the design and development plan and schedule, launch readiness and the supply and support commitments, and leads discontinuance with customers and service teams.
Discipline codes
Owns the business case, the application profile, the program plan, the datasheet and the long-term supply commitment, and leads end-of-support decisions with customers.
Discipline codes
Plans and runs each project on the tailored process: scope, estimates, schedule, resources, interfaces and commitments, the risk register and its treatments, and progress reporting, adjusting the plan when reality moves.
Discipline codes
Leads the cross-functional team, owns the quality planning timing chart against the customer's program milestones, runs the phase reviews with management, tracks open issues and keeps the customer informed of status.
Discipline codes
In: APQP lifecycle
Owns why the platform exists and whether it pays: the business case across the product family, the roadmap, approval of derivatives, roadmap reviews and the platform's retirement.
Discipline codes
Runs the product's outsourced manufacturing chain: production node, unit cost and supply plan, mask and wafer orders, the first build, packaging and test suppliers, and supply resilience.
Discipline codes
The three measures a chip design is usually judged and traded off on.
Design and verification
Sets performance and power targets from the architecture and tracks them through RTL, emulation and physical design to correlation on silicon.
Discipline codes
In: SoC lifecycle
Implements the product on the production node: floorplan and trials from the test chip correlation, then synthesis, test insertion, place and route, timing, power and physical sign-off.
Discipline codes
Owns the power product as a business: target applications and customers, the choice between silicon, silicon carbide and gallium nitride, the business case and pricing, the roadmap of voltage classes and generations, the datasheet, the supply commitment and the decision to discontinue.
Discipline codes
Qualification has passed, the datasheet and production test program are released, supply is ready and the part is released for volume orders.
Gate codes
In: Product lifecycle, SoC lifecycle, AMS lifecycle, Chiplet lifecycle, FPGA lifecycle, Automotive lifecycle, AI accelerator lifecycle, Startup lifecycle, Memory lifecycle, Photonics lifecycle, MEMS and sensors lifecycle, RF lifecycle, Equipment lifecycle, Medical lifecycle, Industrial lifecycle, System lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
The production design kit, with final models and rules correlated to risk production silicon and validated sign-off decks, is released for production tape-outs.
Gate codes
The production software is released with production-signed images, the SDK, documentation, the software bill of materials and licence compliance, and the update service is ready.
Gate codes
The step is released in the production flow for every team within its qualified scope, with controlled documentation, training, capacity and an approved production environment.
Gate codes
Qualification has passed, customers have approved the part for production, for automotive through the production part approval process, and the part is released for volume orders with a supply commitment.
Gate codes
Before the security release, a public way to report vulnerabilities, a disclosure policy and a staffed incident response procedure are in place for the product.
Gate codes
The standard process set, tools and training are released for use by every project in scope.
Gate codes
The item is approved to leave development: production controls protect it, keys are provisioned securely, and monitoring, incident response and updates are ready.
Gate codes
A periodic review shows the certified system is performing: customer scorecards, problem solving closure, layered process audits, contingency plan tests and improvement projects are on track.
Gate codes
In: QMS lifecycle
Owns production transition, manufacturing and test procedures, first article inspection, production test correlation with qualification, and the production release of conforming units.
Discipline codes
Designs the manufacturing route across wafer fab, bump, assembly and test sites: process flow, process instructions, line layout, equipment and tooling, and leads the process FMEA with quality engineering.
Discipline codes
In: APQP lifecycle
List prices, volume pricing rules, channel margins and the ordering information are approved against the standard cost, ready for publication at the launch review, so quotes and the launch price list rest on the margin the business agreed.
Gate codes
Brings the process into the kit: device targets and design rule intent from the technology definition, baseline silicon and test structure measurements, and qualification results and process changes later.
Discipline codes
In: PDK lifecycle
Develops and integrates the wafer process: implantation and activation, gate oxide and interface treatment, trench etch where used, ohmic and Schottky contacts, passivation and field plates for gallium nitride, thinning and backside metal, and transfers the process to larger wafers and qualifies later process changes.
Discipline codes
Sources the tools and materials: long-lead orders, purchase specifications and acceptance terms, supplier risk and single sources, export control classification and licences for tools and technology, materials declarations such as RoHS and REACH, delivery logistics, and the supply agreements and supplier reviews the running fab depends on.
Discipline codes
Develops, freezes and sustains the MEMS process: films and their stress, deep etching, release, anti-stiction treatment, bonding and cavity sealing, with the design rules and control structures, and qualifies process changes.
Discipline codes
Timing, power and physical checks are clean on the final layout, and the layout matches the netlist.
Gate codes
Enough early money, from founders, angels, a grant or an accelerator programme, is committed to pay for the proof of concept, with what it must show agreed in advance.
Gate codes
The fab starts product wafers for customers, with its quality system certified, operations ready and customers qualifying their products.
Gate codes
A recurring review of complaints, vigilance reports, trends, vulnerability findings, field actions and changes confirms the benefit-risk balance still holds, updates the risk management file and decides any corrective action or design change.
Gate codes
The certification plans and the plans and standards under them are complete, consistent with each other, submitted to the certification authority or the integrator, and reviewed at the first stage of involvement.
Gate codes
The production part approval package is complete at the required submission level, every element has been checked against the customer specific requirements, the part submission warrant is signed and the package is submitted.
Gate codes
In: APQP lifecycle
Firmware and the main software run on emulation or FPGA prototypes of the hardware, the main use cases have been exercised, and the hardware and software issues found are tracked to closure.
Gate codes
In: System lifecycle
Owns the product's security: the security plan and secure development lifecycle, the review board, the release decision, residual risk acceptance and the security support plan until the end of support.
Discipline codes
Plans and runs post-market surveillance: complaint handling, trend analysis, vigilance reporting, field safety corrective actions, periodic reports, component obsolescence watch and the records archive at end of support.
Discipline codes
Protects the item in production: the cybersecurity control plan, secure provisioning of keys and certificates, end-of-line configuration and locking, protection of production tools and data, and the release for post-development.
Discipline codes
Leads disciplined problem solving for customer complaints, internal escapes and audit findings: containment, root cause by occurrence and escape, corrective and systemic preventive action, verification and closure, and the warranty and returns analysis that feeds it.
Discipline codes
In: QMS lifecycle
Owns the threat model, the security architecture, secure boot and update, security testing, the software bill of materials and the response to vulnerabilities until the end of support.
Discipline codes
In: System lifecycle
Chooses the product package and test strategy from the test chip experience, designs the package, develops the test program and qualifies the product through outsourced assembly and test suppliers.
Discipline codes
Measured performance and efficiency on the target workloads are compared with the targets and the model, and the remaining gaps have owners and plans.
Gate codes
Design partners have evaluated the test chip or platform on their own problems and stated in writing what value they saw, what they need changed and whether they intend to buy the product.
Gate codes
The production trial has shown that the process meets its requirements at rate: measurement systems are acceptable, initial capability on special characteristics meets the customer's requirement, production validation and qualification tests are passed, packaging is evaluated and the production control plan is approved.
Gate codes
In: APQP lifecycle
Units built on the production line, with production tooling, test and suppliers, meet the requirements and the target yield, so the system is ready for production release.
Gate codes
In: System lifecycle
Codes the rules as design rule check, layout versus schematic, antenna, density and electrical rule check decks for each supported tool category, and proves each check on pass and fail test layouts.
Discipline codes
In: PDK lifecycle
Verifies the platform as a whole and owns the conformance test suite every derivative must pass to stay on the platform.
Discipline codes
The checks and reviews that show a product or a kit meets its requirements before release.
Quality and reliabilityDiscipline codes
Runs advanced product quality planning under IATF 16949, the design and process FMEAs, the control plan and the production part approval submission, and keeps statistical process control running in production.
Discipline codes
Checks the kit as a whole: a library of QA test cases and QA designs run through every supported tool category, regression on every change, and the checks that the parts of the kit agree.
Discipline codes
In: PDK lifecycle
Assesses how much confidence the tool needs and how its errors would be detected, writes the human review policy, controls the flow documentation, runs incident and corrective action handling and change impact assessment, and records lessons learned.
Discipline codes
Defines the screening flow and lot acceptance tests, plans and runs qualification to the agreed framework, and reports lot acceptance for every flight lot.
Discipline codes
In: Space lifecycle
The equipment has passed the environmental and electromagnetic qualification tests in its specification, with deviations dispositioned, and the reliability and derating analyses support the safety assessment.
Gate codes
Quality planning for the part is closed: process performance meets the goals, customer feedback is acted on, and lessons learned are recorded and fed into the next program.
Gate codes
In: APQP lifecycle
Sets and audits the software process: the quality plan, coding standard, static analysis and coverage rules, licence compliance for third-party and open-source code, and the process and safety evidence some markets require.
Discipline codes
Keeps the tool's configuration known and controlled: design reviews, configuration baselines from alpha onward, the record of what each customer qualified, change notification agreements, field change orders and customer change notices, corrective actions and the final archive.
Discipline codes
Plans product quality, prepares production part approval and the control plan where customers need them, runs field return analysis and corrective action, and issues change and discontinuance notices.
Discipline codes
Runs the quality management system the design sits in: design control procedures, document and record control, design reviews, supplier and purchasing controls, the design history file and device master record, internal audits, CAPA and management review.
Discipline codes
Runs the system day to day for top management: context analysis, gap assessment, the implementation plan, the risks and opportunities register, objectives tracking, certification body liaison and the transition to revised standards.
Discipline codes
In: QMS lifecycle
Runs advanced product quality planning, design and process FMEAs, the compliance register for qualification standards, RoHS, REACH and export classification, customer-specific requirements, audits and the production part approval process, field monitoring and returns analysis, process change notices to customers and the records kept to the end of supply.
Discipline codes
Sets up the quality management system, plans yield learning, sets the defect baseline, qualifies process reliability, supports customer product qualification and certification, and drives yield and quality in operation.
Discipline codes
The software requirements, the supported platforms, the support period and the quality plan are agreed with product management and engineering.
Gate codes
A memory generation, its density points and the interface standards it will follow are put on the roadmap, and a team is funded to define it.
Gate codes
In: Memory lifecycle
The mission profile, voltage class, current rating, switching conditions, ruggedness needs and target cost are agreed with the business and lead customers and baselined as the product requirements.
Gate codes
A new package technology is placed on the packaging roadmap, with the customer drivers behind it, and a development team is funded to define it.
Gate codes
The product may ship from a security point of view: requirements met or risks accepted, certificates and declarations in place, provisioning running, incident response ready and customers given what they need to integrate it securely.
Gate codes
Hazards and threats are analysed, the risk reduction the product must provide is decided, and the target integrity and security levels are agreed with the customer or the system owner.
Gate codes
The platform roadmap, the lead product and the first derivatives, with their cost, schedule and resources, are agreed and the platform's development is committed.
Gate codes
Classifies the device in each market, sets the regulatory strategy and applicable standards, prepares technical documentation and submissions, deals with notified bodies and authorities, and assesses every later change for its regulatory effect.
Discipline codes
The mission profile, radiation environment and quality level are agreed with the customer and baselined, so every later design and test decision can be traced to them.
Gate codes
In: Space lifecycle
The sensing specification and the environmental and mission profile are agreed and placed under change control, so transducer, process and ASIC work design to the same targets.
Gate codes
The RF requirements are baselined: every band, power, sensitivity, linearity, efficiency and coexistence target is written with how it will be verified, and the regulatory regimes of each market are known.
Gate codes
In: RF lifecycle
Security requirements are written from the threat model, each traced to its threat and to the verification that will prove it, and placed under change control.
Gate codes
The process, performance, productivity, cost, safety and factory interface requirements are written, traced to customer needs and agreed as the baseline for concept work.
Gate codes
Hardware and software requirements are complete, traced to the system requirements, validated, and under configuration control; derived requirements have been reviewed by the safety assessment.
Gate codes
In: Avionics lifecycle, Industrial lifecycle, Automotive SPICE lifecycle
The system requirements and use cases are reviewed and placed under change control, so architecture, hardware and software teams work to one agreed set.
Gate codes
In: System lifecycle
Specifies and delivers the reference and evaluation boards the software is brought up, validated and shipped on, with their debug access, power measurement points and board files.
Discipline codes
The product runs at a steady state: yield and cost are at or near plan, delivery is reliable, early field issues are closed or contained, and sustaining owners take over.
Gate codes
In: Product lifecycle, Process node lifecycle, Memory lifecycle, Power and compound lifecycle, Fab build lifecycle, MEMS and sensors lifecycle, Package technology lifecycle, Structured ASIC lifecycle
Users have moved off the step, data held by the supplier is deleted or returned with confirmation, licences are closed and the records needed to reproduce past results are archived.
Gate codes
The part's radiation response is measured and reported, compared with the predictions, and the hardness level the part can be supplied to is agreed.
Gate codes
In: Space lifecycle
A tool programme is opened against named customer technology roadmaps, with a sponsor, a core team and funding to define requirements.
Gate codes
The recertification audit is complete before the certificate expires, any transition to a revised standard is done, and a renewed certificate is issued.
Gate codes
In: QMS lifecycle
Works out which security regulations and export rules apply in each market, classifies the cryptographic functions for export, prepares the conformity evidence and declarations, and keeps reporting obligations in the field.
Discipline codes
Owns the radiation environment specification, the technology radiation assessment, the hardening approach, the dose budget, the single-event rate predictions and the radiation hardness assurance plan and report that tie design, test and lot acceptance together.
Discipline codes
In: Space lifecycle
Plans and runs the reliability and qualification work: the design verification plan's stress tests, the qualification plan against AEC-Q100, AEC-Q101, AEC-Q104 or AEC-Q200 as applies, mission profile review, and requalification after changes.
Discipline codes
In: APQP lifecycle
Plans and runs the intrinsic reliability tests, analyses every failure, writes the technology qualification, and runs reliability monitoring and change qualification once the node is in volume.
Discipline codes
Writes how devices and wires age and fail into the kit: ageing and self-heating models, electromigration and current density rules, and the ESD and latch-up rules, from the process reliability data.
Discipline codes
In: PDK lifecycle
Assesses cell and product reliability from test vehicles on, plans and runs component qualification and conformance testing to JEDEC methods, issues materials declarations such as RoHS and REACH, handles customer quality and returns, and requalifies shrinks and changes.
Discipline codes
Sets reliability requirements from the mission profile and proves them: gate oxide lifetime, threshold drift, blocking and humidity stresses, temperature and power cycling, body diode degradation, avalanche, short-circuit and cosmic ray robustness, failure analysis, lifetime models, module qualification and requalification of later changes.
Discipline codes
Sets reliability requirements from the mission profile, runs early stress on prototypes, plans and runs qualification for the MEMS, ASIC and package together, analyses every failure, and monitors reliability in volume.
Discipline codes
Plans and runs component-level and board-level reliability tests, analyses every failure with the failure analysis lab, writes the technology qualification report and supports customers' product qualifications.
Discipline codes
Suppliers for every die, the interposer, the substrate, assembly and test are agreed, with their quality expectations.
Gate codes
The kit for the node is approved and funded: which devices, options, design styles and customers it serves, and who owns it.
Gate codes
In: PDK lifecycle
The round that pays for product silicon is signed and received, with a development plan, budget and runway that reach first revenue, and a board that has approved the product plan.
Gate codes
A shrink, a layer or bits per cell step, or a derivative is approved with its cost per bit case and its requalification scope.
Gate codes
In: Memory lifecycle
The starting material is specified and at least one qualified source, internal or external, is committed in the volumes and at the quality the plan needs.
Gate codes
The overall scope, the application profile, the certification schemes and markets, and the plans for functional safety and security management are agreed, so every later activity has an owner and a standard.
Gate codes
The processes in scope, the target capability level for each, the organisational unit, the projects, the plug-ins and the model version are agreed with the sponsor and, where the customer requires it, with the customer.
Gate codes
The scope of the system, its sites and remote support functions, the products and the standards applied are agreed, with the quality policy and the register of customer specific requirements.
Gate codes
In: QMS lifecycle
Designs the software stack and agrees the hardware-software interface with the chip architects: memory map, registers, interrupts, the split between boot ROM, firmware and drivers, and the change control that keeps both sides aligned.
Discipline codes
Designs the root of trust, secure boot chain, key storage, isolation and lifecycle states from the security requirements, allocating every requirement to an architecture element and keeping the security architecture in step with the chip architecture.
Discipline codes
Carries out the quantitative and qualitative safety analyses: the safety concept, FMEDA and hardware metrics, dependent and common cause failures, and the safety manual's conditions of use.
Discipline codes
Decides how the system is built: its block structure, the chips and modules it uses, which functions go into silicon, programmable logic, firmware or software, and the interfaces between them.
Discipline codes
In: System lifecycle
Bench measurements across conditions are explained against simulation, and the device models are updated where they differ.
Gate codes
In: AMS lifecycle
The seed round is signed and the money received, with a plan and runway that reach test chip results and the next round, and the board and reporting set up that investors expect.
Gate codes
The part has been measured against its specification with fixture effects removed, and measurements agree with simulation closely enough to trust the models, or every difference is explained and recorded.
Gate codes
In: RF lifecycle
Support ends as announced: last-time-buy orders are filled, open service commitments are closed, and design and service records are archived for as long as they must be kept.
Gate codes
A surveillance audit is complete and any nonconformities are closed, so the certificate stays valid until the next audit.
Gate codes
In: QMS lifecycle
The fabric and the hard IP have been measured across voltage, temperature and process corners, and the measured delays have been compared with the pre-silicon timing models.
Gate codes
Owns the threat model, the security architecture of the software stack, secure boot and secure update, the signing service and key management, and the security review before release.
Discipline codes
Secures the path from design data to the customer: IP and component provenance, protected mask and test data, key generation and injection, device identity and certificates, lifecycle locking and counterfeit prevention at every site.
Discipline codes
Owns the platform threat model and security architecture, reviews reused IP, and answers for vulnerabilities across every product that shares the platform until its end of support.
Discipline codes
Plans and allocates substrate, epitaxy, wafer fab and assembly capacity, models cost per die and per module, builds the business case for wafer size moves and second sources, runs the cost-down programme and the last-time-buy and final builds.
Discipline codes
Chooses and contracts the wafer, assembly and test suppliers, plans demand and capacity, makes production ready, runs the ramp and steady-state supply, and plans the final builds and any bridge supply at end of life.
Discipline codes
Qualifies substrate and material suppliers, plans capacity across tools and sites, secures long-term supply agreements for volume, tracks supply risk and plans the run-out of materials at end of life.
Discipline codes
For stacked products such as HBM, the stack architecture, base die interface, through-silicon via plan and bump map are frozen as product design starts, before the core and base die designs close, so the package and interposer partners can design against them.
Gate codes
In: Memory lifecycle
Packages what customers develop with: compiler toolchain and debugger support for the chip's cores, the SDK libraries, headers and examples, middleware, connectivity stacks and reference applications.
Discipline codes
The silicon has been attacked as the threat model expects an attacker would, protocol interoperability is shown, and every weakness found is fixed, mitigated or recorded as accepted security errata.
Gate codes
Defines the item or its out-of-context assumptions, carries out the hazard analysis, writes the safety concepts and hardware safety requirements, and runs the FMEDA, fault tree and dependent failure analyses.
Discipline codes
Owns the requirements and how the tool meets them: the system architecture, the split into subsystems, the interfaces between them, the performance error budget, the cost of ownership model and requirements traceability from customer need to test evidence.
Discipline codes
Turns user needs into design inputs, owns the system architecture, interfaces and essential performance definition, keeps the trace from user needs to design outputs and verification, and writes the design verification report.
Discipline codes
Runs the secure development process and the security risk work: threat and risk assessment, security requirements and architecture, security verification, user guidance, vulnerability handling and security updates for the support period.
Discipline codes
Elicits stakeholder requirements, derives and analyses system requirements, designs the system architecture and allocates requirements to hardware and software, integrates and verifies the system, and keeps traceability from stakeholder needs to system tests.
Discipline codes
Protects the design in the field: bitstream encryption and authentication, key provisioning in production, and a safe route for field updates.
Discipline codes
In: FPGA lifecycle
Classifies the design data involved, approves what may go where for the pilot and for production, assesses the supplier's hosting and access controls, sets up the environments and confirms deletion at retirement.
Discipline codes
Selects suppliers for their cybersecurity capability, agrees cybersecurity interface agreements with customers and suppliers, including chip and IP suppliers, flows requirements down, collects their evidence and keeps vulnerability and incident contacts working in both directions.
Discipline codes
Production has shown the agreed stability, so the extra launch checks are removed with the customer's agreement and the part runs under the normal production control plan.
Gate codes
In: APQP lifecycle
Screens suppliers and in-house options, manages the supplier relationship and agreement, plans licence and compute capacity, tracks supplier change notices and closes licences at retirement.
Discipline codes
Agrees with each software, IP and hardware supplier what processes, work products and evidence they provide, monitors their progress and quality, takes in their deliveries and checks them, and includes their capability in the organisation's own.
Discipline codes
The certification body's first stage audit has confirmed the scope, documentation and readiness, and any areas of concern are addressed before the second stage.
Gate codes
In: QMS lifecycle
Assesses the supply continuity of the technology, package and materials, plans die and wafer banks, runs the obsolescence watch and the regular supply reviews, keeps counterfeit avoidance and traceability in place through authorised supply, and closes supply through the last-time buy and final lots.
Discipline codes
In: Space lifecycle
Plans the supply life, approves long-life components and second sources, watches components, processes and tools for obsolescence, and runs change notification, last-time buys and redesign decisions.
Discipline codes
The human review policy and accountability matrix are approved: who reviews AI-assisted outputs, with which checks, and which named engineer signs off each deliverable that includes them.
Gate codes
The platform software, firmware, SDK and build system are feature complete on the virtual platform, and a derivative configuration can be built from them.
Gate codes
Owns the decision to adopt, fund, continue or retire the step, the business case behind it and the approval of the data and IP position and the accountability matrix.
Discipline codes
Owns the reason for the program, funds it, removes blockers, accepts the scope and the outcome, and reviews whether capability holds once the assessment is over.
Discipline codes
The shrink or derivative is characterised and requalified, customers are notified of the change and those who need to have requalified it.
Gate codes
In: Memory lifecycle
Parts built on the production line, in the flight package and screened to the flight flow, start qualification to the agreed framework.
Gate codes
In: Space lifecycle
Brings the sub-tier suppliers into the plan: wafer foundry, assembly and test subcontractors, substrates, materials and services, with their own approvals, FMEAs and control plans, and the flow-down of customer specific requirements.
Discipline codes
In: APQP lifecycle
Approves and monitors suppliers, including foundries, assembly and test subcontractors and materials suppliers, flows customer requirements down, audits suppliers and develops those that need it.
Discipline codes
In: QMS lifecycle
A site is chosen against the site requirements, with its energy, water, workforce, infrastructure, supply chain, sustainability and incentive position assessed and the land secured or under option.
Gate codes
The security support plan, certificates and regulatory reports are reviewed against the products still in the field.
Gate codes
Owns the allocated system requirements, the functional hazard assessment, the preliminary and final system safety assessments, the assurance level allocation and the safety review of derived requirements, design changes and in-service problems.
Discipline codes
Specifies, sources and qualifies the starting material: silicon carbide crystal growth and wafering, epitaxial layers with their doping and defect limits, gallium nitride epitaxy on its host substrate and silicon wafers for silicon devices, with supplier audits, incoming inspection, supply agreements, larger-diameter substrates and second sources.
Discipline codes
Onboards customers to each release, answers their questions, logs and tracks errata, and sends update releases and impact statements to the users they affect.
Discipline codes
In: PDK lifecycle
Plans and secures supply across photonic wafers, electronic wafers, lasers, fibres and assembly, sets up the ramp, and runs the last-time buy and the archive.
Discipline codes
Writes the boot code, board support package, drivers and application software that run on the FPGA's processor or a processor beside it.
Discipline codes
In: FPGA lifecycle
Writes the prototype and test chip software and the evaluation software design partners run.
Discipline codes
Builds and maintains the software that runs the tool and connects it to the fab: sequencing, recipes, interlock logic, process control, alarms and the user interface, data collection, the factory host interface to the public SEMI standards, remote service access and equipment cybersecurity.
Discipline codes
Plans and develops firmware and device software under IEC 62304 for its safety class, from software requirements and architecture to unit, integration and system testing, software of unknown provenance, the software bill of materials, release and maintenance.
Discipline codes
Owns the software development plan and standards, the high-level and low-level requirements, the architecture, the source code and the executable object code, following DO-178C at the assigned level.
Discipline codes
Develops the embedded firmware, safety software, communication stacks and update mechanism to the integrity level and the secure development process, with qualified tools and a software bill of materials.
Discipline codes
Derives and analyses software requirements, designs the software architecture and detailed design, writes the units, and keeps them consistent and traceable to the system requirements and architecture.
Discipline codes
Specifies, builds and fixes the security software: secure boot stages, cryptographic services, secure onboard communication, diagnostics access control, intrusion detection sensors and logging, under secure coding rules.
Discipline codes
Builds the operating system, middleware and applications of the system, starting on models before hardware exists and continuing through validation, release and updates.
Discipline codes
In: System lifecycle
Builds the shared software base: operating system support, middleware and libraries, with the configuration options each derivative selects, and maintains it for every product on the platform.
Discipline codes
Builds the experimental flow used to explore the fabric, then adds the device to the vendor's design software: device model, synthesis and packing, placement, routing, timing analysis, power estimation and bitstream generation, with timing data that moves from advance to production.
Discipline codes
Builds executable models of the chip, such as SystemC transaction-level models, to explore the architecture and to give software teams a virtual platform long before RTL is ready.
Discipline codes
In: SoC lifecycle
Designs the accelerator card or module, its power delivery from the rack to the die, and its air or liquid cooling, and builds the bring-up and production boards.
Discipline codes
Writes the sensing specification and the system error budget from the target applications, supports lead customers with evaluation kits, application notes and datasheets, and feeds field performance back.
Discipline codes
Turns the requirements into an architecture and a link budget, splits the system targets into block specifications, and keeps the budget honest as simulation and measurement results come in.
Discipline codes
In: RF lifecycle
Plans and runs validation of the link in the target system: evaluation platforms, bit error rate and margin, conformance to the named optical interface standards, interoperability testing with transceiver and host partners, laser safety classification, customer support and application notes.
Discipline codes
The last parts are tested and the program, patterns, hardware design data and test data are archived for the retention period, so a later question can still be answered.
Gate codes
The founders agree that the problem is real, stated by potential customers in their own words, large enough to build a company on and solvable with a chip they can make, and decide to form a company around it.
Gate codes
The business approves moving the device or platform to a larger substrate diameter, with a business case, a transition plan and the customer notification approach agreed.
Gate codes
An installed tool passes its site acceptance test and the customer's process acceptance, and the customer signs final acceptance, which starts warranty and service.
Gate codes
Threat analysis and risk assessment is complete for the item, every risk has a treatment decision, and later changes to the TARA go through review.
Gate codes
Identifies the assets, describes the attackers and their access, maps the attack surface, rates each risk and records how it is treated, writes the security requirements from the risks to mitigate, and keeps the threat model current as the design and public attacks change.
Discipline codes
The design meets every timing constraint on the chosen device and a bitstream is built from the frozen, signed-off source.
Gate codes
In: FPGA lifecycle
The product's test approach is accepted in outline: the quality level the market expects, the cost of test the business case can carry, and a test team named to work with design from the start.
Gate codes
The process technologies, wafer size, capacity, product mix and phasing the fab is planned around are chosen, with a first tool list and wafer cost estimate.
Gate codes
Classifies the tool, its spares, upgrades, software and technical data under the export control rules of every country involved, screens customers, end uses and end users, obtains and tracks licences, controls technology shared with partners and remote service access, and keeps the records the rules require.
Discipline codes
Plans and designs the test vehicles, measures their device, defect and memory structures on wafer, and supplies the parametric data that models, yield and qualification depend on.
Discipline codes
Develops the production test program with the screening automotive customers expect, such as outlier screening and tests at more than one temperature, and runs yield and test data analysis in production.
Discipline codes
Plans how the test chip is packaged and tested through outsourced assembly and test suppliers, and delivers packaged test chips for evaluation.
Discipline codes
Writes installation specifications, moves tools in, connects, starts up and accepts them with their suppliers, qualifies them on wafers, then raises and holds equipment availability, and removes or transfers tools at the end.
Discipline codes
Plans electrical test of the test vehicles, including die-to-die interface tests against UCIe where it is used, defines incoming die and known good die requirements with die suppliers, builds the test flow for stacked and multi-die packages and releases production test.
Discipline codes
The process meets its intrinsic reliability targets on qualification vehicles built on the frozen baseline, and the technology qualification report is approved.
Gate codes
The locked tool, model and settings meet the success criteria on the full reference design set, their failure modes are catalogued with the check that catches each one, and the scope the qualification covers is stated.
Gate codes
The tools needed for the first full-flow lots have passed acceptance, safety sign-off and wafer qualification, and are connected to factory automation.
Gate codes
Test vehicles built on the frozen baseline pass the component-level and board-level reliability tests in the plan, every failure has been analysed, and the technology qualification report is approved.
Gate codes
Sets what the test must screen for each market, reviews coverage and screening before release, and owns excursions, test escapes and customer returns with their corrective actions.
Discipline codes
Builds the reference design set and success criteria, measures accuracy, repeatability and failure modes against known answers, and reruns the references on a schedule and after every change.
Discipline codes
Owns the assessment of every design and verification tool, the qualification of tools whose output is not otherwise verified, using DO-330 for software tools, and control of the design environment so builds can be reproduced.
Discipline codes
The transducer layout is checked against the MEMS design rules and the multiphysics model, and the MEMS mask set is released for prototype wafers.
Gate codes
A periodic review decides whether to extend the technology with new options, reduce its cost, move it to new sites, or plan its successor and withdrawal.
Gate codes
Representative units built on the production process, with a reviewed type test plan agreed with the test laboratories and certification bodies, are ready for validation and type testing.
Gate codes
Everything needed for a significant production run at the planned rate is ready: production tooling and equipment, released test programs and fixtures, trained operators, production materials from approved suppliers and the pre-launch control plan in use.
Gate codes
In: APQP lifecycle
A gate that checks the technology is ready before the next commitment.
Gate codes
Used in: SoC lifecycle: Technology feasibility, SoC lifecycle: Tape-out technology readiness, SoC lifecycle: Qualification passed, Soft IP lifecycle: Technology feasibility, Soft IP lifecycle: IP verification sign-off, Hard IP lifecycle: Technology feasibility, and 71 more
Identifies assets and damage scenarios, describes threat scenarios and attack paths, rates impact and attack feasibility, determines risk and records treatment decisions, and keeps the TARA current as the design and the threat landscape change.
Discipline codes
Tests every wafer and part: wafer-level parametric and blocking tests, high-current and high-voltage final test, dynamic tests where needed, screening such as gate stress or burn-in where the plan requires it, outlier detection and the test data that yield and quality teams rely on.
Discipline codes
Probes the MEMS and ASIC wafers, measures prototypes, characterises the sensor across temperature, supply and stimulus, and builds the production test program, limits and test capacity.
Discipline codes
Plans how every part is tested, mostly by loading test configurations that exercise the fabric, routing and memories, with scan and built-in self-test for the hard IP, and releases the binning and production test programs.
Discipline codes
Builds the test architecture into the base array and its fixed layers, and proves it on base wafers and the validation vehicles, so every customer design's test is built on it.
Discipline codes
Prepares and maintains the regulatory evidence: CSMS and SUMS certificates of compliance, the vehicle type approval documentation for UN R155 and UN R156, contact with the approval authority and technical service, and reporting of monitoring results.
Discipline codes
Brings up the first silicon in the lab and checks it against the specification.
Discipline codes
In: SoC lifecycle
Brings up first silicon, characterises it across temperature and supply corners, and tests every safety mechanism on silicon.
Discipline codes
Designs the lab and test boards, brings up the test chip, measures it against the model, writes the lessons for product silicon and builds the evaluation kits design partners use.
Discipline codes
Design validation on production-equivalent units and the summative usability evaluation show the device meets user needs and intended use, residual risk is judged acceptable against benefit, and the risk management report is approved.
Gate codes
Every safety function is validated, and the EMC, electrical safety, environmental, explosion protection and interoperability tests are passed, with the reports needed for certification.
Gate codes
Review pilot outputs independently, define the independent check that catches each failure mode, update verification sign-off criteria and review errors found during first use.
Discipline codes
Proves the system meets its requirements: the validation plan, functional, performance, power, thermal, reliability and software testing on the design and production validation builds, and pre-compliance checks.
Discipline codes
In: System lifecycle
Output scales up towards forecast demand as design wins move into production, with yield, delivery and early field quality watched closely.
Gate codes
In: Product lifecycle, SoC lifecycle, Photonics lifecycle, Power and compound lifecycle, MEMS and sensors lifecycle, RF lifecycle, System lifecycle, FPGA chip lifecycle, Structured ASIC lifecycle
Test capacity, hardware sets, operators and data monitoring are ready for volume, so the ramp is not limited by test.
Gate codes
Units built to the released design, characterised chips, released software and approved test plans are available, so design verification and type testing at the laboratory can start on a known configuration.
Gate codes
Vulnerabilities found in the field are reviewed: each has been analysed against the TARA and managed, and monitoring results are reported where required.
Gate codes
Receives and triages vulnerability reports, coordinates fixes and disclosure, runs the update delivery service, and watches the third-party and open-source components in the software bill of materials.
Discipline codes
Assesses the workforce a site can supply, plans hiring, training and certification ahead of each phase, works with universities, colleges and public programmes on the skills pipeline, and reviews workforce health in operation.
Discipline codes
Packaging steps done on the whole wafer before it is cut into dies.
Manufacturing, test and packaging
Develops the wafer-level modules: under-bump metallurgy, solder bumps and copper pillars, redistribution layer lithography, plating and dielectrics, fan-out reconstitution and moulding, and panel-level variants where used.
Discipline codes
Gate and discipline codes are plain initials chosen for the Hub's charts, not any company's internal codes. Standard names belong to their publishers; the guides explain them in our own words. Missing an abbreviation? Suggest one.