Component · Test & DFT
Scan flip-flop
A flip-flop with a multiplexer on its data input that selects between the functional path and the scan input from the previous cell in the chain. It costs a little area and delay in exchange for full controllability and observability of that state bit.
- Also known as
- Scan cell, Mux-D flop, SDFF
- Type
- Component
- Domain
- Test & DFT, DFT architecture
Notes
The mux-D style dominates; older LSSD latch-based designs used separate scan clocks instead.
Related terms
- Scan chain
- Scan enable
- Full scan
- Standard cell
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