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Writing the product requirements, deciding what goes in FPGA logic, in a processor and in software, and choosing an FPGA family and device by its logic, memory, I/O, power, cost and expected availability.
Where this stage sits
This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.
Key0.0Planned0.3Early draft0.5Draft0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateYou are here: Requirements & Device SelectionAI impactDDisruption (red)AAugmentation (blue)OOpportunity (green)How AI is changing the workWhat the steps meanWhat the codes mean
Requirements & Device Selection: maturity 0.0, Planned. Product requirements split between FPGA logic, processors and software, and the device chosen with its availability checked.A
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System & FPGA Architecture: maturity 0.3, Early draft. Architecture, clocking and reset plan and pin assignment baselined at the pin-out freeze; later changes go through change control.A
RTL & HLS Design: maturity 0.5, Draft. Architecture clarified as the logic is written and the board is released, with every change controlled.
Requirements & Device Selection: maturity 0.0, Planned. Block list, IP core needs and a logic resource and effort estimate agreed with the system architect for the device selection; no code yet.
System & FPGA Architecture: maturity 0.3, Early draft. Block design, IP core choices and pin assignment agreed for the pin-out freeze.
RTL & HLS Design: maturity 0.5, Draft. Main blocks written and integrated with the IP cores, running in simulation and trial builds, while the board is released.DAAO
Requirements & Device Selection: maturity 0.0, Planned. Verification approach agreed: simulation, clock domain crossing and lint checks, any reused verification IP and an effort estimate; no plan yet.
System & FPGA Architecture: maturity 0.3, Early draft. Environment: verification plan drafted from the architecture; testbench structure, verification IP and coverage model planned.
RTL & HLS Design: maturity 0.5, Draft. Environment: testbench, checkers and verification IP running on the integrated blocks, with coverage collection, lint and clock domain crossing checks started.A
System & FPGA Architecture: maturity 0.0, Planned. Vendor tool version, build flow and timing headroom target agreed for the chosen device, with the draft pin plan run through the tool's pin checks; no design built yet.
RTL & HLS Design: maturity 0.3, Early draft. First trial builds of the growing design show its fit and early timing on the chosen device.
Requirements & Device Selection: maturity 0.0, Planned. Board approach, form factor and first power and thermal estimate agreed.
System & FPGA Architecture: maturity 0.3, Early draft. Schematics drawn around the frozen pin assignment, with power rails and clocking in place.A
RTL & HLS Design: maturity 0.5, Draft. First board revision laid out, analysed for signal and power integrity, and released for fabrication and assembly.A; Board data released (milestone for one item)
Requirements & Device Selection: maturity 0.0, Planned. Software scope agreed for the hardware and software partitioning: the processor, operating system and drivers needed, with an effort estimate; no interface defined yet.
System & FPGA Architecture: maturity 0.3, Early draft. Software interface specification agreed for the registers, interrupts and memory map the logic provides; driver design started against it.
RTL & HLS Design: maturity 0.3, Early draft. Software interface specification agreed for the registers, interrupts and memory map the logic provides; driver design started against it.D
RTL & HLS Design: maturity 0.0, Planned. Debug features the board needs agreed with the board team before its release: test points, debug headers and configuration access; no bring-up plan yet.
RTL & HLS Design: maturity 0.0, Planned. Compliance standards for the target markets and the system test approach agreed; the board design reviewed for compliance risks before release.
Requirements & Device Selection: maturity 0.0, Planned. Security needs that steer the device choice agreed: bitstream encryption and authentication, key storage and field update support; threat analysis to follow.
System & FPGA Architecture: maturity 0.3, Early draft. Threat analysis done and security requirements agreed for the configuration, the keys and field updates.
RTL & HLS Design: maturity 0.3, Early draft. Threat analysis done and security requirements agreed for the configuration, the keys and field updates.
Requirements & Device Selection: maturity 0.0, Planned. Device availability, its own lifecycle and the supply route checked.
System & FPGA Architecture: maturity 0.0, Planned. Device availability, its own lifecycle and the supply route checked.
RTL & HLS Design: maturity 0.3, Early draft. Board components checked for availability and manufacturability, with a first approved component list at board release.