Design Technology Co-Optimization: jointly tuning process/device/interconnect options and design rules with design intent — standard cell height and track count, pin access, MOL rules, backside power, via pillar strategy — so a node's PPA is optimized for the actual designs it will carry.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Senior role at the boundary of process integration, standard-cell/library design and physical design, typically at a foundry, IDM or library team; years of node-development participation.
Register version 1.