Custom Layout Engineer

Project

Work done for a product or program.

• Create full-custom layouts in Virtuoso for amplifiers, bandgaps, PLLs, SerDes, ADC/DAC, and IO cells.
• Apply matching techniques including common-centroid, interdigitation, dummy devices, and guard rings.
• Plan block-level floorplan, device orientation, and routing to minimise parasitic mismatch and coupling.
• Run and clean DRC, LVS, antenna, and density checks iteratively during layout construction.
• Execute post-layout parasitic extraction and hand results to designers for simulation-driven layout revisions.
• Implement latch-up, ESD, and well-proximity precautions in accordance with foundry design rules.
• Build parameterised cells and layout generators in SKILL or Python to accelerate repeated structures.
• Manage layout-dependent effects such as stress, WPE, and LOD that shift device behaviour at advanced nodes.
• Integrate custom blocks into the digital top level including pin alignment, power rails, and abstract generation.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain layout databases, version control, and reuse libraries across derivative products.

Project

1. Produce and hand over the role's key deliverables
   • DRC/LVS-clean custom block GDS layout
   • Post-layout extracted netlist for designer simulation
   • Layout abstract views and integration collateral
   • Parameterised cell and layout generator scripts
   • Matching and device placement strategy documentation
2. Implement the layoutGeneral
   • Floorplan and plan the power grid
   • Place, build the clock tree and route
   • Run extraction and analysis
3. Close sign-offGeneral
   • Close timing at every corner
   • Clear DRC and LVS
   • Complete the sign-off checklist

Function

1. Maintain the flowGeneral
   • Update scripts and flow settings
   • Qualify new tool versions
2. Share knowledgeGeneral
   • Document fixes for recurring issues
   • Train newer engineers on the flow