Also known as: Design for Manufacturability Engineer; Yield Enhancement Design Engineer; Litho-Aware Design Engineer
See this role on the Process node lifecycle or on the PDK lifecycle or on the SoC lifecycle
Improves manufacturability and parametric yield of the layout by applying litho-aware, CMP-aware, and random-defect-aware design techniques before the design reaches the fab.
Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction
The role's tasks, work products, gates, skills, career paths, listings and pay benchmarks are for registered members. Registration is free and takes a minute. You come back to this page afterwards.