ESD and Latch-up Physical Verification Engineer

Project

Work done for a product or program.

• Run ESD path resistance and latch-up checks on full-chip layouts.
• Verify ESD device placement, bus resistance and IO ring integrity.
• Check topological ESD rules using foundry or custom decks.
• Analyse CDM and HBM discharge paths and voltage overstress.
• Debug flagged violations with layout and IO designers.
• Support qualification testing and failure analysis correlation.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain ESD rule decks and methodology for each node.

Project

1. Produce and hand over the role's key deliverables
   • ESD and latch-up check reports
   • ESD verification methodology
   • Rule deck updates
   • Violation debug notes
2. Support programsGeneral
   • Agree what each program needs
   • Deliver in time for milestones
3. Manage issuesGeneral
   • Track requests to closure
   • Escalate risks

Function

1. Run the functionGeneral
   • Maintain policies and processes
   • Keep records and controls
2. ImproveGeneral
   • Report performance
   • Lead improvement work