Warpage

Notes

The dominant yield issue in large body and thin packages, since a warped part will not wet all its joints during reflow.

Overview

Warpage is the bending of a die, substrate, wafer or finished package out of flat, caused mainly by layers that expand and shrink by different amounts as temperature changes. It is specified in micrometres across the part, often at several temperatures through the solder reflow profile, because too much warpage stops solder joints forming properly and can crack dies or layers.

How it works

A package is a sandwich of materials: silicon, copper, organic substrate, mould compound, underfill and solder. Each has its own coefficient of thermal expansion. When the stack heats up during assembly or reflow and cools down again, layers that want to expand by different amounts pull on each other, and the package bends, often into a smile or frown shape. The shape can change with temperature, flipping direction between room temperature and reflow.

Warpage causes problems at several stages. Thin wafers and reconstituted fan-out wafers can warp too much to handle, and dies can shift during moulding. In assembly, a warped package may not touch the board evenly during reflow, causing open joints or bridging. Over the product's life, stresses from mismatch can crack solder or delaminate layers.

Engineers measure warpage with optical methods such as shadow moiré, at temperatures through the reflow profile, and predict it with finite element simulation that uses temperature-dependent material properties. They control it by choosing mould compounds and substrates with matched expansion, balancing copper across substrate layers, adding stiffeners, and adjusting die and package thickness.

Examples

• A large flip-chip package whose corners lift during reflow, causing open solder joints at the edge.
• A fan-out wafer that warps after moulding, fixed by changing the mould compound.
• Shadow moiré measurements of a package from room temperature to peak reflow temperature.
• Simulating a system-in-package strip to choose material properties before building samples.

Why it matters

Larger packages, thinner dies and multi-die assemblies all make warpage harder to control, and it is a frequent cause of assembly yield loss. Package design and materials engineers, assembly process engineers, reliability engineers and board assembly teams all deal with it, and it constrains package and substrate choices for large AI and server chips.

In the chip lifecycle warpage is predicted during package design, measured during package development and qualification, and monitored in production through incoming checks and assembly yield.

Related terms

• CTE
• EMC
• PoP
• Head-in-pillow

Where it appears on the Hub

Used on 37 pages of the Hub. In each group, the pages that mention it most come first.