Co-optimizing die and package as one system: bump and pad-ring planning, power delivery split across die grid, package and board, signal escape and routing feasibility, warpage and CTE-driven mechanical stress, and thermal path allocation.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Physical design or package role on a flip-chip or 2.5D product, learned by iterating with the package designer under real constraints.
Register version 1.