Also known as: Substrate Layout Designer; Package Layout Designer; Package CAD Designer
See this role on the Chiplet lifecycle or on the Package technology lifecycle or on the SoC lifecycle
Executes the physical layout of package substrate and RDL layers — trace routing, plane shaping, via placement and impedance control — to design intent and supplier capability. Is the hands-on craftsperson who makes dense escape patterns physically real.
Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction
The role's tasks, work products, gates, skills, career paths, listings and pay benchmarks are for registered members. Registration is free and takes a minute. You come back to this page afterwards.