Testbench

Notes

Testbench code routinely exceeds the RTL it verifies by three to five times in line count.

Overview

A testbench is the verification code that surrounds a design under test: it generates input stimulus, models the world around the design, checks the outputs and collects coverage. It is never built into the chip. Modern chip testbenches are mostly written as SystemVerilog classes following UVM, rather than the simple Verilog modules once used.

How it works

The name comes from the lab bench of signal generators and oscilloscopes used to test hardware; today almost all functional verification happens in simulation. A testbench has a few standard parts. Stimulus generators create input transactions, often with constrained randomisation so the simulator produces many legal variations. Drivers turn transactions into signal activity on the design's ports, and monitors watch the ports and turn activity back into transactions.

Checking compares observed behaviour with the expected result. A scoreboard collects expected outputs from a reference model and matches them against what the design produced, and assertions watch for protocol rules being broken. Functional coverage records which scenarios and values have occurred, showing how much of the verification plan has been exercised.

Good testbenches are reusable. Components for a standard interface, such as AXI or PCI Express, are written once and reused across blocks and projects, and the same environment can grow from block level to subsystem and full chip. Testbench performance also matters, because regressions run thousands of tests on large compute farms every night.

Examples

• A UVM testbench for a memory controller with a reference model and scoreboard checking every read.
• A small Verilog testbench that applies a few directed patterns to a new arithmetic block.
• Reusing licensed verification IP for a USB interface inside a chip-level testbench.
• Running a regression of thousands of randomised tests overnight and reviewing coverage holes in the morning.

Why it matters

Verification takes a large share of chip development effort, and the testbench is where most of it goes. Design verification engineers build and run testbenches, verification methodology engineers set their structure, and verification IP developers supply reusable components. A weak testbench can pass a buggy design.

In the chip lifecycle testbenches are built during design, grow through block, subsystem and chip verification, and are reused for derivative products and debugging silicon issues.

Related terms

• DUT
• UVM environment
• BFM
• Reference model

Where it appears on the Hub

Used on 46 pages of the Hub. In each group, the pages that mention it most come first.