Functional verification exists to answer one question with confidence, not just hope: does this RTL actually do what the specification says, and just as importantly, does it never do what it shouldn't? On a modern SoC, verification effort routinely exceeds RTL design effort, because proving a design correct across its entire input space is a fundamentally harder problem than writing the design in the first place.
A good verification effort doesn't just check the RTL against itself. The testbench is built as a separate, independent interpretation of the specification, ideally by someone other than the RTL author. If the same engineer misreads a spec while writing both the RTL and the checker, the bug sails through undetected. Reusable testbench architectures (commonly built around methodologies like UVM) let a scoreboard independently predict expected behavior and flag any mismatch against what the design actually produced.
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