Test time

Notes

Scan compression, chain balancing and higher shift frequencies attack it from the design side; multisite attacks it from the equipment side.

Overview

Test time is the time a chip occupies the tester during production test, including applying patterns, making measurements, waiting for signals to settle and moving parts in and out. Because tester time is expensive and charged by the second, test time is one of the main drivers of test cost and one of the variables design for test and test engineers work hardest to reduce.

How it works

Each part passes through a test program of many tests: continuity and leakage checks, scan patterns, memory built-in self-tests, analogue and radio measurements, and functional checks. The time for each depends on the amount of pattern data, the speed at which it can be shifted in and out, measurement settling, and the number of times the tester must reconfigure. Handler or prober index time, the time to swap one device for the next, adds to it.

Several levers reduce it. Scan compression shrinks the amount of test data that must pass through the tester's limited pins. Built-in self-test moves pattern generation onto the chip. Multisite testing tests many devices in parallel, so the time is shared. Test engineers reorder flows so that the tests most likely to fail run first, and drop or sample tests that never fail, while watching that quality is not compromised.

Test time interacts with quality targets. Automotive and safety parts often need more patterns, tests at several temperatures and burn-in, all of which add time, while consumer parts are squeezed hard for cost.

Examples

• Increasing scan compression so that pattern data per part drops sharply without lowering fault coverage.
• Moving from testing four devices at a time to sixteen to cut effective time per part.
• Running the tests that most often fail at the start of the flow so that bad parts are rejected sooner.
• Removing a redundant analogue measurement after months of data show it never catches a failure missed by others.

Why it matters

For high-volume chips, saving a fraction of a second per part adds up to significant money and tester capacity. DFT engineers, test engineers, product engineers and test cost analysts trade test time against coverage and quality, and the economics of test are changing as devices become more complex and quality expectations rise.

In the chip lifecycle test time is estimated during DFT planning, measured on first silicon, optimised through ramp, and reviewed throughout production.

Related terms

• Cost of test
• Scan compression
• Multisite test
• SLT

Where it appears on the Hub

Used on 34 pages of the Hub. In each group, the pages that mention it most come first.