Also known as: Automatic Test Pattern Generation Engineer; Pattern Generation Engineer; Test Pattern Engineer
See this role on the Test program lifecycle or on the SoC lifecycle or on the Soft IP lifecycle
Generates the manufacturing test patterns that detect silicon defects, maximising fault coverage per pattern while fitting tester memory and test time budgets.
Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction
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