Multisite test

Notes

Site counts of 16 to 512 are common for simple parts; parallel efficiency falls when analog resources or serial operations cannot be duplicated.

Overview

Multisite test is the practice of testing several devices at the same time on one automatic test equipment (ATE) system, with each device, or site, connected to its own set of tester resources through a shared probe card or load board. Because the tester and handler time is shared across all sites, it is the main way manufacturers reduce the cost of test per device. Site counts range from two for very complex processors to hundreds or thousands of dies for memory tested at the wafer.

How it works

The test programme is written once and applied to every site in parallel. The tester supplies enough instruments, such as digital channels, power supplies and analogue or RF resources, for each site, or shares some resources between sites through multiplexing on the test board. Results are logged per site, and failing sites are binned while the others continue.

Perfect parallelism would mean that adding sites adds no test time. In practice some steps run one site after another, for example when an instrument is shared, when per-site calculations for trimming or repair are done serially, or when the software handles sites in sequence. The industry measures this with multisite efficiency, which compares the multisite test time with the single-site time and the number of sites: 100 per cent means no extra time, and 0 per cent means the sites might as well have been tested one after another.

Higher site counts bring physical limits. Handlers have a fixed number of test positions for a given package size, probe cards and boards must stay stiff and make reliable contact across more sites, routing becomes harder, and thermal control must be uniform. On the factory floor, engineers also watch for site-to-site differences in yield or measurements, because one site behaving differently often points to a probe card or contact problem rather than to the silicon.

The right number of sites is an economic choice that balances tester and interface cost, efficiency and throughput for each product.

Examples

• Full-wafer probing of DRAM, where thousands of dies are contacted and tested in parallel.
• A large high-performance processor tested two at a time because each device needs so many tester channels and so much power.
• A low-cost microcontroller tested at a high site count because its simple pin needs let many devices share one tester.
• Yield analytics showing that one site on a probe card has a statistically different failure rate, prompting a probe card inspection.

Why it matters

Test engineers, test hardware designers and test cost and capacity planners decide site counts and tune programmes for parallel execution, because test cost per unit feeds directly into product margins and selling price. A poorly balanced multisite set-up can deliver far less saving than the site count suggests, or hide yield problems behind one bad site.

In the chip lifecycle, multisite capability is planned with DFT and test strategy at architecture, built into load boards and probe cards before production, and optimised during ramp and volume production at wafer sort and final test.

It matters most to: ATE Test Program Developer, Final Test Engineer, Load Board and Test Hardware Design Engineer, Test Cost & Capacity Engineer, Test Operations Engineer

Common confusions

Not the same as concurrent test

Concurrent test runs different tests on different blocks of the same device at once. Multisite test runs the same programme on several devices at once; the two are often combined.

Not the same as multi-site manufacturing

In operations, multi-site can mean making a product in more than one factory. In test, a site is one device position on the tester.

Key figures

• 90 to 95 per cent Typical multisite efficiency for RF and SoC device testing according to an Advantest application note; memory testing often comes much closer to 100 per cent. (Source: Multi-Site Efficiency and Throughput (Joe Kelly, application note, first published 2008, revised 2026), 2026-10-22)

Sources

1. Promises and Perils of Parallel Test (Anne Meixner, 10 September 2024) (opens in a new tab), Semiconductor Engineering, 2026-10-22
2. Multi-Site Efficiency and Throughput (Joe Kelly, application note, first published 2008, revised 2026) (opens in a new tab), Advantest, 2026-10-22
3. ATE Implementations for Multisite Device Test (Evaluation Engineering, 1 July 2005) (opens in a new tab), Electronic Design, 2026-10-22
4. Making The Most of Test Resources (Laura Peters, 9 September 2025) (opens in a new tab), Semiconductor Engineering, 2026-10-22

Related terms

• Cost of test
• Test time
• Load board
• Handler

Where it appears on the Hub

Used on 7 pages of the Hub. In each group, the pages that mention it most come first.