SDC (Synopsys Design Constraints)

Notes

Although named after Synopsys, SDC is supported by essentially every vendor and is the closest thing to a universal constraints interchange.

Overview

SDC (Synopsys Design Constraints) is a Tcl-based format for stating a design's timing intent and related conditions, such as its clocks, input and output delays, loads and timing exceptions, so that synthesis, implementation and static timing analysis tools all work to the same requirements. It began as the constraint format of Synopsys tools and is now read by many other tools, including FPGA software and open-source timing analysers. An SDC file does not describe the logic itself; it describes the conditions the logic must meet.

How it works

An SDC file is a sequence of Tcl commands. create_clock defines a clock on a port or pin with its period, and create_generated_clock describes clocks derived from another clock, such as a divided clock. set_input_delay and set_output_delay say how much of the clock cycle is used outside the block, and set_load models what an output drives. set_clock_latency and set_clock_uncertainty add the expected clock delay and a margin for effects such as jitter.

Exceptions change the default rule that every path must complete within one clock cycle. set_false_path removes paths that can never be exercised or that cross between unrelated clocks, set_multicycle_path allows a path several cycles, and set_max_delay and set_min_delay put explicit limits on a path. Synopsys describes SDC as carrying design intent for synthesis, clocking, timing, power, test and operating conditions.

Because SDC is Tcl, files can use variables, loops and queries for design objects. Synopsys makes the format available under an open-source licence through its TAP-in programme, but each tool supports its own subset and extensions; Microchip's Libero software, for example, reads a defined subset of SDC commands for timing. Constraints that work in one tool can therefore be read differently, or ignored, in another. A mistaken exception is risky: an over-broad false path tells every tool to ignore a path that may really matter.

Examples

• A create_clock command that defines a 1 GHz core clock as a 1 ns period on the chip's clock input port.
• A set_false_path between two clock domains that are joined only through synchronisers, which a CDC tool checks separately.
• A set_multicycle_path that lets a slow arithmetic block take two clock cycles to produce its result.
• An FPGA project in Microchip's Libero software importing an SDC file to drive its timing analysis.
• OpenSTA reading a gate-level Verilog netlist, Liberty libraries and SDC constraints to report timing in an open-source flow.

Related terms

• create_clock
• False path
• Multicycle path
• Timing exception
• MCMM
• Clock uncertainty

Where it appears on the Hub

Used on 21 pages of the Hub. In each group, the pages that mention it most come first.