Standard · Verification & Validation
SDF (Standard Delay Format)
An IEEE-standard ASCII file that carries cell and interconnect delays, timing checks and path constraints from a timing tool into a simulator. Annotating SDF turns a zero-delay netlist simulation into a timing-accurate one.
- Also known as
- IEEE 1497, .sdf
- Type
- Standard
- Domain
- Verification & Validation, Simulation
- Also relevant to
- EDA Tools & Flows
Notes
SDF timing-check violations in gate-level runs are a classic source of false failures caused by unrealistic testbench clocking.
Related terms
- GLS
- Static timing analysis
- RTL simulation
- Waveform
- SPEF
- Verilog netlist
Part of the Verification & Validation glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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