Term · EDA Tools & Flows
False path
A timing exception marking a structural path that can never be functionally sensitised, so the timer should ignore it. It is used for mutually exclusive mode logic, test-only paths and synchroniser crossings.
- Also known as
- set_false_path
- Type
- Term
- Domain
- EDA Tools & Flows, Timing constraints
- Also relevant to
- Physical Design & Signoff
Notes
Over-use of false paths is a common way teams accidentally hide real violations from signoff.
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Part of the EDA Tools & Flows glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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