Term · Design & Architecture
Floorplan
The early spatial plan of a die, allocating area and location to blocks, memories, I/O and power structures. At architecture level it validates that the chosen partitioning is physically feasible.
- Also known as
- Chip plan
- Type
- Term
- Domain
- Design & Architecture, SoC architecture
- Also relevant to
- Physical Design & Signoff
Notes
Architects use a rough floorplan early to catch wire-length and aspect-ratio problems that block-level thinking hides.
Overview
A floorplan is the plan of where the major parts of a chip go on the die: the size and shape of the die and core, the positions of large blocks and memories, the I/O pads, and the main power distribution structures. Architects use an early floorplan to check that a proposed partitioning will physically fit and meet its targets, and physical design teams refine it into the starting point for placement and routing. A good floorplan keeps blocks that exchange a lot of data close together and leaves enough room for wiring.
How it works
Floorplanning starts with an area estimate: the cells and macros each block needs, plus space for routing, which together with a target utilisation and aspect ratio set the die and core dimensions. I/O pads are placed around the edge, and large fixed-size blocks, such as SRAMs, analogue circuits, clock generators and hard IP, are positioned so that critical paths stay short, wiring does not jam in narrow channels, and heat is spread across the die.
The core is then divided into rows of standard cell sites, tap cells and well ties are inserted, and the power grid is laid out so that every cell can draw current without excessive voltage drop. In large SoCs the floorplan is usually hierarchical: the chip is split into partitions that separate teams implement in parallel, each with a fixed outline, pin positions and timing budgets, so moving one boundary late can ripple into its neighbours.
Data flow increasingly drives these choices. In a 2023 Semiconductor Engineering article, a Siemens EDA technologist pointed out that how fast data moves between two functional modules depends on where they physically sit, and the article described floorplanning as becoming a more creative, architecture-level task rather than a routine step before place and route.
Examples
- A mixed-signal chip that keeps sensitive analogue blocks and their pads together in one region, away from noisy digital logic.
- A block-level floorplan created in OpenROAD from a target utilisation and aspect ratio, followed by I/O pin placement and power grid creation.
- A processor core floorplan with its caches next to the units that use them most, reviewed by architects before the RTL is complete.
- An accelerator floorplan that places compute tiles around on-chip SRAM so that heavily used data paths stay short.
Why it matters
Chip architects, floorplanning engineers and physical design leads own the floorplan, and it shapes almost every later result: die size and therefore cost, how hard timing closure will be, routing congestion, power integrity and thermal behaviour. Problems found late, such as a memory placed far from the logic that uses it, can force significant rework.
Related terms
Part of the Design & Architecture glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 34 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
Roles
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary