Roles / Chip Architect

Chip Architect

ARC-002v1

System & SoC ArchitectureArchitectureIC6–IC8 / M3–M5IC or manager

Also known as: Silicon Product Architect; Product Line Architect; Lead Chip Architect

See this role on the SoC lifecycle or on the Soft IP lifecycle or on the Chiplet lifecycle or on the Automotive lifecycle or on the Startup lifecycle or on the Space lifecycle or on the Medical lifecycle or on the Industrial lifecycle or on the Automotive SPICE lifecycle or on the System lifecycle or on the Platform lifecycle or on the FPGA chip lifecycle or on the Structured ASIC lifecycle or on the Hard IP lifecycle

Summary

Owns the definition of a whole silicon product — feature set, die plan, packaging, process node and derivative strategy — bridging business case and engineering execution. Ensures the chip that ships is the chip the market will buy.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Select the process node and foundry offering in partnership with technology and supply teams, weighing cost per mm2 against performance gain.
Set the die plan, floorplan intent, package selection and pin budget together with package and physical design leads.
Own the cost model covering die area, yield assumptions, package, test time and bill-of-materials impact.
Define the derivative and binning strategy so one die can serve multiple SKUs and market segments.
Chair the product architecture review and approve or reject feature requests against schedule and area budget.
Drive customer-facing architecture engagements and translate lead-customer feedback into architecture commitments.
Define the silicon feature list that marketing collateral, datasheets and product briefs will be built from.
Manage the architecture risk register including IP maturity, process readiness and second-source exposure.
Lead post-silicon competitive benchmarking and feed learnings into the next-generation product definition.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Define the product feature set and competitive positioning against named competitor parts and their published benchmarks.

Major tasks

Project

Produce and hand over the role's key deliverables

Product architecture definition document and feature list
Die plan, package selection and pin budget
Silicon cost and yield model with SKU derivation plan
Competitive benchmarking and positioning analysis
Product architecture risk register
Executive architecture review decks and gate approvals

Define the architectureGeneral

Collect and clarify the product requirements
Build performance and power models
Write and baseline the architecture specification

Support implementationGeneral

Answer specification questions from design and verification
Assess the impact of proposed changes
Compare results with the original targets

Function

Build the architecture practiceGeneral
- Keep modelling tools and reference models current
- Publish design guidelines and specification templates
Plan aheadGeneral
- Study workload and technology trends
- Contribute to the product roadmap

Works with

Product management and marketing
business unit GM
SoC architects
foundry account teams
packaging and OSAT partners
key customers
finance
program management

Typical backgrounds

MS or PhD in Electrical Engineering or Computer Engineering, often with an MBA; 12–20 years including SoC architecture and direct customer exposure.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

4 / 5

Remote feasibility

Medium

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Santa Clara and San Diego USA; Hsinchu Taiwan; Bangalore India; Eindhoven Netherlands; Munich Germany; Seoul South Korea; Shanghai China

Certifications / standards training

—

Transfers to (industries)

Hyperscale cloud custom silicon programs, automotive tier-1 electronics, consumer electronics platform definition

Risk if vacant

Feature scope drifts without a cost or margin anchor and the product ships late, over-area, or mispositioned against the competition.

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