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Extracting the layout's parasitics and rerunning the key simulations with them, and checking electromigration, IR drop, ESD protection and reliability before release.
Where this stage sits
This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.
Key0.0Specified0.3Sketched0.5Draft0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: Post-Layout Verification & Sign-offAI impactDDisruption (red)AAugmentation (blue)OOpportunity (green)How AI is changing the workWhat the steps meanWhat the codes mean
Custom Layout: maturity 0.8, Feature complete. Layout complete and matching the schematics; matching and sensitive nodes reviewed with the layout designers.
Custom Layout: maturity 0.8, Feature complete. RF layout complete, with electromagnetic models of the drawn passives and interconnect.A
Post-Layout Verification & Sign-off: maturity 1.0, Complete. RF performance with electromagnetic models and extracted parasitics meets the link budget; the design then supports measurement on silicon.
Tape-out or SoC Hand-off: maturity 1.0, Complete. RF performance with electromagnetic models and extracted parasitics meets the link budget; the design then supports measurement on silicon.
Tape-out or SoC Hand-off: maturity Freeze, Frozen. Design kit version locked with the tape-out; device models are compared with silicon and updates go into a new kit version.
Custom Layout: maturity 0.8, Feature complete. Post-layout test benches ready and run on the complete layout's first extractions.
Post-Layout Verification & Sign-off: maturity 1.0, Complete. Simulations on the extracted layout meet the specification across corners: post-layout sign-off.
Custom Layout: maturity 0.8, Feature complete. Layout drawn and clean for design rules and layout versus schematic; matching review held.DA; Layout freeze (milestone for one item)
Custom Layout: maturity 0.3, Sketched. Measurement needs, test points and bench approach agreed with the circuit and layout designers.
Post-Layout Verification & Sign-off: maturity 0.5, Draft. Characterisation plan drafted from the post-layout results; evaluation board designed.
Tape-out or SoC Hand-off: maturity 0.8, Feature complete. Characterisation plan final at tape-out, with bench, boards and measurement scripts ready for first silicon.
Custom Layout: maturity 0.0, Specified. Likely qualification standard and the ESD and latch-up levels the protection being drawn must meet reviewed with layout; no mission profile or plan yet.
Post-Layout Verification & Sign-off: maturity 0.3, Sketched. Qualification standard, mission profile and ESD and latch-up targets set from the sign-off results.
Tape-out or SoC Hand-off: maturity 0.5, Draft. Qualification plan drafted at tape-out, with stresses, sample sizes and boards.
Custom Layout: maturity 0.5, Draft. Requirements confirmed against the verified circuit; lead customers engaged.
Post-Layout Verification & Sign-off: maturity 0.8, Feature complete. Preliminary datasheet drafted from the post-layout results; sampling plan agreed.
Tape-out or SoC Hand-off: maturity 0.8, Feature complete. Preliminary datasheet drafted from the post-layout results; sampling plan agreed.
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