DRAM Array & Periphery Design Engineer

Project

Work done for a product or program.

• Define mat and subarray size, cells per bitline and open- versus folded-bitline architecture to trade array efficiency against bitline capacitance ratio.
• Build array efficiency models that account for sense amplifier stripes, subword drivers, redundancy overhead and periphery area, and drive die-size targets.
• Floorplan bank groups, global and local data lines, column select paths and the centre-strip periphery for the target package and pinout.
• Co-optimise the array pitch with process integration and lithography to fit the design rules of the target node such as 1-beta or 1-gamma.
• Define the bank-level timing architecture including tRRD, tFAW, tCCD and refresh grouping to meet JEDEC bandwidth requirements.
• Model and mitigate row-to-row and bitline coupling, wordline resistance and local IR drop across the array with distributed RC simulation.
• Specify the redundancy architecture — number of spare rows and columns, repair granularity and fuse budget — with test and yield engineering.
• Run array power modelling for activate, refresh and page-hit traffic and feed the IDD budget to circuit and product teams.
• Lead die-size and array efficiency reviews with the technology, design and product planning organisations.
• Correlate silicon bit-fail maps and array yield learning back into the next-generation array architecture proposal.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain design guidelines, coding standards and reusable blocks.General
• Improve design flows and checks with the CAD and methodology teams.General
• Mentor newer engineers and share lessons learned across projects.General

Project

1. Produce and hand over the role's key deliverables
   • Array architecture specification with mat, subarray and bank organisation
   • Array efficiency and die-size model with sensitivity analysis
   • Bank and periphery floorplan with global data line routing plan
   • Redundancy and repair architecture definition
   • Array RC and coupling simulation signoff reports
   • Next-generation array architecture proposal deck
2. Design the blockGeneral
   • Write or capture the design to the specification
   • Run lint, simulation or circuit checks
   • Close design reviews and their actions
3. Support integration and sign-offGeneral
   • Fix bugs found by verification
   • Support timing and physical closure
   • Deliver handoff files and documentation

Function

1. Keep design methods currentGeneral
   • Maintain coding and design standards
   • Build and maintain reusable blocks
2. Develop peopleGeneral
   • Mentor newer engineers
   • Run design reviews and knowledge sharing sessions