Choosing the storage cell and how cells are organised: for DRAM the capacitor and access transistor structure, the bit line and word line scheme and the array to periphery split; for NAND the cell type, bits per cell, layer count direction and the array under or beside the periphery; with bank, page and plane organisation, redundancy and error correction budget, die size and bits per wafer estimated for each option.
This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.
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