Running simulation on the post-synthesis or post-layout netlist with SDF back-annotation to catch what RTL simulation cannot: X-propagation and reset initialization, scan and DFT mode behavior, power-up sequencing, and timing-sensitive integration bugs before tapeout.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Learned in DV or DFT by owning the pre-tapeout GLS gate, where X-debug against a gate netlist teaches the skill faster than any course.
Register version 1.