Mask cost

Notes

A full advanced-node mask set runs into the tens of millions of dollars, which is why low-volume designs stay on mature nodes.

Overview

Mask cost is the price of the full set of photomasks needed to manufacture a chip design, one mask for each patterned layer, and it is one of the largest fixed costs of taking a design to silicon. It rises steeply at advanced nodes because designs need more masking layers, multiple patterning and extremely precise, defect-free EUV masks. Because it is paid again for every new design or respin, it shapes decisions about prototyping, design reuse and when to fix bugs.

How it works

A photomask (also called a reticle) is a quartz plate carrying the pattern for one layer of the chip, which the lithography scanner projects onto the wafer. A complete process needs one mask for every patterned layer, so the mask count follows the process and has grown node by node, especially where multiple patterning splits one layer across several masks. Each critical layer needs advanced writing, inspection and repair, and leading-edge masks increasingly use complex curvilinear shapes that are harder to write and inspect.

The set is a non-recurring engineering (NRE) cost: it is paid once per design revision, regardless of how many wafers are made. Where a late fix can be made in a few upper metal layers, only those masks need replacing, which is one reason teams try to keep late changes there. At high volume the cost per chip is small; for a low-volume product or a prototype it can dominate.

Two trends complicate the picture. Industry experts note that EUV masks have shorter lifetimes in production, so they must be replaced more often and become partly a recurring cost. And to make prototyping affordable, foundries run multi-project wafer services in which many designs share one mask set and its cost.

Examples

• A chip company prototyping on TSMC's CyberShuttle multi-project wafer service, sharing a mask set to cut prototyping costs.
• A respin limited to two metal layers so that only those masks have to be remade.
• An EUV mask replaced during high-volume production because its usable life has ended.

Why it matters

Mask cost is a key input to any decision to tape out a new chip, to respin it, or to prototype on an advanced node. Product managers, programme managers and finance teams build it into business cases; design teams plan metal-fix strategies and spare cells to avoid full respins; and mask ordering specialists and photomask engineers manage the sets themselves.

In the chip lifecycle, mask cost is committed at tapeout, recurs with every respin or engineering change, and returns during production when masks wear out or new revisions are released.

It matters most to: FP&A Analyst (Semiconductor Business Unit), Mask Ordering and Procurement Specialist, Mask Shop Interface Engineer, NPI Program Manager (Silicon), Photomask Engineer

Common confusions

Not the same as total NRE

Mask cost is one part of non-recurring engineering cost, alongside design labour, EDA tools, IP licences and verification. Planning only for the masks understates what a new chip costs to develop.

Not the same as wafer cost

Wafer cost is paid for every wafer processed and grows with volume. Mask cost is largely fixed per design revision, whatever the volume.

Not the same as mask in the data-hiding sense

In security, masking is a countermeasure that randomises data inside a circuit to resist side-channel attacks. It has nothing to do with photomasks.

Key figures

• About 40 mask layers at 45/40 nm and about 60 at 14/10 nm Figures quoted by Kelvin Low of Samsung foundry in 2016, who expected roughly 80 to 85 layers at 7 nm if immersion lithography were stretched without EUV. (Source: Mask Maker Worries Grow (Mark LaPedus, 18 August 2016), 2026-10-22)

Sources

1. Disruptive Changes Ahead For Photomasks? (Gregory Haley, 25 June 2025) (opens in a new tab), Semiconductor Engineering, 2026-10-22
2. Mask Maker Worries Grow (Mark LaPedus, 18 August 2016) (opens in a new tab), Semiconductor Engineering, 2026-10-22
3. CyberShuttle prototyping service (opens in a new tab), TSMC, 2026-10-22

Related terms

• NRE
• Tapeout
• Respin

Where it appears on the Hub

Used on 6 pages of the Hub. In each group, the pages that mention it most come first.