Wafer map

Notes

The visual pattern usually points at the responsible tool or step faster than any numerical summary does.

Overview

A wafer map is a picture or data file showing, die by die, the result of a test or inspection at each position on a wafer, such as pass or fail, a bin number or the location of a defect. Its first practical job is to tell assembly which dies to pick and package. Its second is diagnostic: the spatial pattern of failures often points to the process step or tool that caused them.

How it works

At wafer sort the tester records a result for every die, usually a bin code that says whether the die passed and, if not, which test it failed. Failing dies were once marked with a dot of ink; today the results are kept in an electronic map file that travels with the wafer, and at assembly the die attach equipment reads the map and picks only the good dies. The SEMI E142 standard defines how such substrate maps are structured and exchanged, including an XML schema and messages between factory host systems and equipment, and it covers frames, strips and trays used in packaging as well as wafers.

Engineers also read maps for patterns. Common signatures have names: a centre cluster, a ring of failures around the edge, a localised patch near the edge, a donut, a scratch, a random scatter, or an almost fully failing wafer. These shapes help narrow down causes, since a radial or edge pattern points towards process uniformity, a line towards a scratch, and a pattern that repeats in every exposure field towards the reticle or lithography.

Classification is increasingly automated. A widely used public dataset, WM-811K, holds about 811,000 wafer maps, of which about 173,000 are labelled with pattern classes, and much research applies machine learning to it. Class imbalance and similar-looking classes, such as edge patches and scratches, remain difficult.

Examples

• A sort map in which failing dies form a ring at the wafer edge, prompting a check of an edge-sensitive process step.
• An electronic map passed from the tester to the die attach machine so that only passing dies are picked for packaging.
• A SEMI E142 map in XML exchanged between a factory host and assembly equipment through the GEM interface.
• Machine learning models trained on the public WM-811K dataset to sort maps into eight failure patterns.
• A stacked map of a whole lot showing a failure cluster that repeats in the same place in every exposure field.

Why it matters

Wafer maps are one of the most used views in yield work. Product and test engineers use them to set and check bins, yield analysts and data scientists mine them for signatures, process engineers use them to confirm a fix, and assembly relies on them to avoid packaging bad dies, which matters even more when several dies share one package.

In the chip lifecycle, wafer maps first appear at wafer sort on first silicon, are studied intensely through yield ramp, and are produced for every wafer in volume production, feeding both assembly and yield monitoring.

It matters most to: Product Engineer, Test Data Analytics & Yield Engineer, Wafer Sort Engineer, Yield Analytics Engineer, Yield Data Scientist

Common confusions

Not the same as bin map

A bin map is a wafer map whose values are test bin codes. Wafer map is the broader term and also covers maps of inspection defects or measured values.

Not the same as an inspection defect map

An inspection map shows physical defect locations found during processing; a sort map shows electrical results. Overlaying the two helps show which defects actually kill dies.

Not the same as memory map

In software and chip architecture, a memory map lists address ranges. A wafer map is a spatial picture of results across a wafer.

Related standards

• SEMI E142 (substrate map data for wafers, frames, strips and trays)

Sources

1. SEMI E142: Specification for Substrate Mapping (opens in a new tab), SEMI, 2026-10-22
2. SEMI E142: Specification for Substrate Mapping (standards introduction) (opens in a new tab), PDF Solutions, 2026-10-22
3. Semiconductor Wafer Bin Map Defect Pattern Classification based on Transfer Learning Considering Data Class Imbalance (Inyoung Park and Jeeyoung Kim, 2024) (opens in a new tab), Journal of the Korea Academia-Industrial cooperation Society, 2026-10-22
4. Bridging Quantum Computing Paradigms toward Semiconductor Yield: A Controlled CV-versus-DV Comparison on Wafer-Map Defect Classification (Yeonhong Kim and others, 1 July 2026) (opens in a new tab), arXiv, 2026-10-22
5. Wafer testing (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• Signature analysis
• Bin map
• Edge exclusion
• Reticle field

Where it appears on the Hub

Used on 13 pages of the Hub. In each group, the pages that mention it most come first.