Standard · Design & Architecture
TileLink
An open chip-scale interconnect protocol defined by SiFive, with uncached and cache-coherent tiers, designed alongside RISC-V cores and the Chisel generator ecosystem.
- Type
- Standard
- Domain
- Design & Architecture, Interconnect and fabric
Notes
Common in open source RISC-V SoCs, usually bridged to AXI at the boundary so commercial IP can be attached.
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