Glossary comparison
SystemVerilog vs Verilog: what is the difference?
The difference
Verilog is the older language that SystemVerilog extends and, since 2009, contains. Code written in Verilog is generally valid SystemVerilog.
SystemVerilog is the superset that now contains Verilog, adding classes, assertions, coverage and richer design constructs. Most new code is SystemVerilog even when people call it Verilog.
The two terms
SystemVerilog
The IEEE 1800 hardware description and verification language that extends Verilog with classes, constrained randomisation, functional coverage, assertions and interfaces.
Verilog
A hardware description language using a C-like syntax, standardised as IEEE 1364, used to describe designs at behavioural, RTL and gate level and to write simple simulation testbenches.
Side by side
| Field | SystemVerilog | Verilog |
|---|---|---|
| Stands for | Not an abbreviation | Not an abbreviation |
| Type | Standard | Standard |
| Domain | Verification & Validation | Design & Architecture |
| Group | Testbench & methodology | RTL and HDL |