Closing verification on the frozen test chip RTL, closing timing, power, physical verification and the foundry's checks for the shuttle, checking the RTL on the prototype platform, confirming the shuttle slot and preparing the board, package and lab plan for when silicon returns.

Disciplines

Founders and company strategy^O
- Test Chip Design & Verification: maturity 0.5, Draft. Build or partner choices are recorded and the company roadmap drafted, still resting on the founders' view until silicon and design partners report.
- Test Chip Sign-off: maturity 0.5, Draft. Build or partner choices are recorded and the company roadmap drafted, still resting on the founders' view until silicon and design partners report.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.5, Draft. Build or partner choices are recorded and the company roadmap drafted, still resting on the founders' view until silicon and design partners report.
Customers and design partners^A
- Test Chip Design & Verification: maturity 0.5, Draft. Design partner prospects are in active discussion, with the evaluation each would run outlined.
- Test Chip Sign-off: maturity 0.5, Draft. Design partner prospects are in active discussion, with the evaluation each would run outlined.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.8, Evidence backed. Design partner interest rests on test chip results: an evaluation is signed and run, with results and intent to buy in writing.
Funding and finance^A
- Test Chip Design & Verification: maturity 0.5, Draft. Seed money is managed against runway, with grants applied for and the Series A case outlined around the test chip.
- Test Chip Sign-off: maturity 0.5, Draft. Seed money is managed against runway, with grants applied for and the Series A case outlined around the test chip.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.5, Draft. Seed money is managed against runway, with grants applied for and the Series A case outlined around the test chip.
Legal, IP and agreements^A
- Test Chip Design & Verification: maturity 0.8, Evidence backed. The agreements for the test chip tape-out are signed; design partner terms are negotiated on test chip results and the product IP licences agreed with the product IP sourcing plan.
- Test Chip Sign-off: maturity 0.8, Evidence backed. The agreements for the test chip tape-out are signed; design partner terms are negotiated on test chip results and the product IP licences agreed with the product IP sourcing plan.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.8, Evidence backed. The agreements for the test chip tape-out are signed; design partner terms are negotiated on test chip results and the product IP licences agreed with the product IP sourcing plan.
Program, people and quality^A
- Test Chip Design & Verification: maturity 0.5, Draft. The test chip plan is run, with its risks tracked through tape-out and bring-up.
- Test Chip Sign-off: maturity 0.5, Draft. The test chip plan is run, with its risks tracked through tape-out and bring-up.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.5, Draft. The test chip plan is run, with its risks tracked through tape-out and bring-up.
EDA, compute and design infrastructure^A
- Test Chip Design & Verification: maturity 0.8, Evidence backed. The environment carries the test chip to its RTL freeze, with the design data, tool and kit versions under control.
- Test Chip Sign-off: maturity 1.0, Complete. The environment, kit and libraries carry the test chip through sign-off and tape-out and are proven on its silicon; production licences, compute and the production node design kit are then added for the product and carry it to tape-out.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The environment, kit and libraries carry the test chip through sign-off and tape-out and are proven on its silicon; production licences, compute and the production node design kit are then added for the product and carry it to tape-out.
Architecture and modelling: test chip^A
- Test Chip Design & Verification: maturity 0.8, Evidence backed. The test chip content is held under change control through design, sign-off and tape-out, with the model ready to compare with silicon.
- Test Chip Sign-off: maturity 0.8, Evidence backed. The test chip content is held under change control through design, sign-off and tape-out, with the model ready to compare with silicon.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The model is correlated with test chip silicon and the key claim checked; the evidence goes to the product specification.; Key claim checked on silicon
Proof of concept and FPGA prototyping^A
- Test Chip Design & Verification: maturity 0.5, Draft. A prototype platform for software is in place for the test chip, and the test chip RTL drops are brought up on it.
- Test Chip Sign-off: maturity 0.8, Evidence backed. The frozen test chip RTL runs on the prototype platform and is checked before the sign-off closes.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The prototype has done its job: test chip and evaluation software are checked against the first test chip silicon, and the platform is with the software team for product firmware.
Design and verification: test chip^D
- Test Chip Design & Verification: maturity 0.8, Evidence backed. Results: test chip RTL is complete and frozen, verified against most of its plan, with coverage and regression closure for the sign-off under way.^D
- Test Chip Sign-off: maturity 1.0, Complete. Results: verification is signed off against the plan on the frozen RTL, with coverage and regression goals met for the shuttle.
- Test Chip Tape-out, Bring-up & Evaluation: maturity Freeze, Frozen. Results: the test chip RTL is locked in the shuttle masks; silicon issues are root-caused against it in bring-up, and the lessons and the environment are kept for the product.
IP sourcing and integration: test chip^A
- Test Chip Design & Verification: maturity 0.8, Evidence backed. The test chip IP is licensed and integrated into the RTL at its freeze, and checked through the sign-off.
- Test Chip Sign-off: maturity 0.8, Evidence backed. The test chip IP is licensed and integrated into the RTL at its freeze, and checked through the sign-off.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The test chip IP is shown working on silicon, and the issues found are closed with the providers.
Physical design, DFT and sign-off: test chip^A
- Test Chip Design & Verification: maturity 0.8, Evidence backed. The test chip is implemented on every RTL drop up to the RTL freeze, with timing, power and the foundry's checks closing for the sign-off.^A
- Test Chip Sign-off: maturity 1.0, Complete. The test chip has passed timing, power, physical verification and the foundry's checks on the frozen RTL and is signed off for the shuttle.^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity Freeze, Frozen
Foundry and shuttle operations: test chip^A
- Test Chip Design & Verification: maturity 0.5, Draft. The foundry and shuttle are chosen and the run is booked, with the die area tracked against the design.
- Test Chip Sign-off: maturity 0.8, Evidence backed. The shuttle slot is confirmed with the signed-off die area, and the test chip database is ready to deliver for the run.; Shuttle slot confirmed
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The test chip database is delivered for the run and the test chips come back with their cost and schedule actuals.
Packaging, test and qualification: test chip^A
- Test Chip Design & Verification: maturity 0.5, Draft. Packaging and test suppliers for the test chip are agreed with the partner selection, and the package options checked against the design.
- Test Chip Sign-off: maturity 0.8, Evidence backed. The test chip package plan is ready for the tape-out, and assembly and test are booked for the shuttle return.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The package plan is final at the tape-out, and packaged test chips are delivered and tested for evaluation.
Bring-up, evaluation boards and validation: test chip^A
- Test Chip Design & Verification: maturity 0.5, Draft. The test chip evaluation approach and lab are planned with the test chip content.
- Test Chip Sign-off: maturity 0.8, Evidence backed. The test chip evaluation plan and test board are ready for the tape-out.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. The test chip is measured, its results compared with the model and the lessons for product silicon written, and that evidence carries the evaluation kits for design partners.^A
Firmware, software and tools: test chip^D
- Test Chip Design & Verification: maturity 0.5, Draft. Test chip software is started on the prototype platform and kept in step with the RTL drops.
- Test Chip Sign-off: maturity 0.8, Evidence backed. Test chip software runs on the prototype platform, ready for silicon.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 1.0, Complete. Test chip and evaluation software run on silicon and with design partners.
Architecture and modelling: product chip^A
- Test Chip Sign-off: maturity 0.0, Planned. Product scope set apart from the test chip (what carries over, what the product adds, the likely production node), with the specification owner and plan agreed; no product specification yet.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.3, Early draft. The product specification is outlined from the first test chip results and the partners' needs.
Design and verification: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.0, Planned. Product RTL scope beyond the test chip and the design and verification team for it agreed, with effort estimated; block fixes wait for the test chip lessons.
IP sourcing and integration: product chip^A
- Test Chip Sign-off: maturity 0.0, Planned. IP the product will need beyond the test chip listed, with the licences to extend from shuttle to production terms noted; no product IP evaluated yet.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.3, Early draft. Product IP needs are drawn from the test chip and its first silicon results.
Physical design, DFT and sign-off: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.0, Planned. Implementation effort on the production node and the changes to the shuttle flow estimated, with the team agreed; no product floorplan yet.
Foundry and supply operations: product chip^A
- Test Chip Sign-off: maturity 0.0, Planned. Production node and foundry options for the product scoped with the test chip foundry, with first mask and wafer cost estimates; no supply plan yet.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.3, Early draft. Production node and supplier options are drawn up as the test chip actuals come in.
Packaging, test and qualification: product chip^A
- Test Chip Sign-off: maturity 0.0, Planned. Product package and production test route scoped from the test chip package plan, with first unit cost estimates; no options compared yet.
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.3, Early draft. Product package and test options are drawn from the test chip packaging experience.
Bring-up, evaluation boards and validation: product chip^A
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.0, Planned. Product validation scope and lab needs agreed while the test chip is brought up, with the owner and effort estimated; no validation approach yet.
Firmware, software and tools: product chip^D
- Test Chip Tape-out, Bring-up & Evaluation: maturity 0.0, Planned. Product firmware and software development kit scope agreed from the test chip software in bring-up, with the owner and effort estimated; no plan yet.

Test Chip Sign-off

Test Chip Sign-off

Where this stage sits

Stages

Company, funding and customers milestones

Engineering milestones

Disciplines

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