Process node

Notes

Node names within one foundry are comparable over time; across foundries they are essentially brand names.

Overview

A process node is a named generation of chip manufacturing technology, such as 28nm, 7nm or 3nm, bundling a transistor type, a wiring stack, design rules and a design kit. The number once matched a physical dimension of the transistor, but today it is a generation label: node names are not directly comparable between foundries, and the real measures are density, speed, power and cost.

How it works

Each node is developed as a package. Process engineers define the transistor (planar, FinFET or gate-all-around nanosheet), the steps to build it, and the stack of metal layers above it. From test chips and early wafers they derive design rules, device models and libraries, which the foundry releases to designers as a process design kit. Designers then target that kit, and a design cannot simply be moved to another node without redoing much of the physical work.

For decades, shrinking dimensions gave each new node more transistors per area, higher speed and lower power, in line with Gordon Moore's 1965 observation about component counts doubling. As physical scaling slowed, gains increasingly came from new transistor structures, new materials, design and technology co-optimisation and, more recently, advanced packaging.

Foundries also offer variants within a node, tuned for low power, high performance, radio or embedded memory, and half-node shrinks that reuse much of the earlier design work. Older nodes stay in production for decades for analogue, power and cost-sensitive products.

Examples

• A smartphone SoC built on a leading-edge 3nm-class node for density and power efficiency.
• A microcontroller kept on a 40nm node with embedded flash because cost and qualification matter more than density.
• A foundry offering low-power and high-performance variants of the same node.
• A team estimating the extra mask, IP and verification cost of moving an existing design to a newer node.

Why it matters

Node choice is one of the biggest decisions in a chip project: it sets wafer and mask costs, design effort, available IP and performance. Moving to a new node brings higher costs for masks, tools and verification. Process integration engineers, PDK teams, architects and business leaders all reason in nodes, and analysts use them to compare manufacturers, with the caution that labels differ between companies.

In the chip lifecycle the node is chosen at concept, frozen early in design, and defines the PDK used through signoff and production.

Related terms

• Node naming drift
• Nanometre
• Foundry
• Moore's Law

Where it appears on the Hub

Used on 52 pages of the Hub. In each group, the pages that mention it most come first.