Roles / Process Integration Engineer

Process Integration Engineer

FAB-001v1

Process Technology & Fab OperationsManufacturingIC3–IC7 / M2–M3IC or manager

Also known as: Integration Engineer; Module Integration Engineer; PIE

See this role on the SoC lifecycle or on the Process node lifecycle or on the PDK lifecycle or on the Memory lifecycle or on the Photonics lifecycle or on the Power and compound lifecycle or on the Fab build lifecycle or on the MEMS and sensors lifecycle or on the Package technology lifecycle or on the APQP lifecycle or on the QMS lifecycle

Summary

Owns the end-to-end wafer process flow for a technology node so that hundreds of individual module steps combine into a manufacturable, high-yielding device meeting electrical targets.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Lines tagged General are the Hub's general description of this kind of role, used where the role register has no entry yet. They are kept under review and will be refined.

Project

Work done for a product or program.

Own the master process flow and travelers for a technology node, arbitrating trade-offs between litho, etch, deposition, implant, CMP and thermal modules.
Define and maintain the integration split-lot matrix that resolves cross-module interactions such as gate stack Vt shift versus spacer etch selectivity.
Analyse inline and end-of-line electrical test (WAT/PCM) data to localise integration failures to a specific module or step interaction.
Drive integration bring-up of new device features such as buried power rail, backside contact or high-NA-patterned interconnect from first silicon to baseline release.
Set and negotiate inline process windows, CD targets and overlay budgets with module owners and lithography so the integrated flow closes.
Lead failure analysis loops with PFA/TEM/SEM teams, translating physical cross-sections into process corrective actions.
Review and approve every process change request (ECN) that touches the flow, assessing cross-module risk before release to manufacturing.
Co-own device target delivery with the device engineering team, tuning the flow to hit Ion/Ioff, SRAM Vmin and Rc specifications.
Build and maintain the integration risk register and drive Pareto-ranked yield and parametric learning cycles to closure.
Support technology qualification and reliability sign-off by generating split material for TDDB, HCI, EM and BTI stress studies.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Maintain process specifications, control plans and work instructions.General
Work with equipment and material suppliers on performance and quality.General
Improve cost, cycle time and yield across the operation.General

Major tasks

Project

Produce and hand over the role's key deliverables
- Released master process flow and traveler for the node or derivative
- Integration split-lot DOE plans and readouts
- Inline and WAT process window specification with control limits
- Integration yield and parametric learning Pareto with corrective actions
- Technology qualification integration data package
- Process change request assessments and approvals
Introduce new productsGeneral
- Set up and qualify the process
- Transfer it to production
- Support the ramp
Keep production in controlGeneral
- Monitor statistical process control charts
- Contain excursions
- Close corrective actions

Function

Maintain the process baselineGeneral
- Keep specifications and control plans current
- Manage changes through change control
Improve the operationGeneral
- Reduce cost and cycle time
- Work with suppliers on quality

Works with

Module process engineers (litho
etch
films
implant
CMP)
device engineers
yield enhancement
TCAD
fab equipment engineering
product engineering
design enablement
fab operations management

Typical backgrounds

MS or PhD in Electrical Engineering, Materials Science, Chemical Engineering or Applied Physics; 5–15 years in a wafer fab with module and integration exposure.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

5 / 5

Remote feasibility

Low

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Hsinchu and Tainan, Taiwan; Hillsboro and Chandler, USA; Yongin and Hwaseong, South Korea; Dresden, Germany; Kiryat Gat, Israel; Singapore

Certifications / standards training

Six Sigma Green/Black Belt; SEMI standards training; internal Copy Exactly certification

Transfers to (industries)

Photovoltaic cell manufacturing, MEMS foundries, compound semiconductor and power device fabs, advanced display panel manufacturing

Risk if vacant

Module teams optimise locally, cross-module interactions go undetected and the node misses its yield and electrical entitlement milestones.

Register or sign in to read on

The role's tasks, work products, gates, skills, career paths, listings and pay benchmarks are for registered members. Registration is free and takes a minute. You come back to this page afterwards.