Roles / PDK & Design Kit Release Manager

PDK & Design Kit Release Manager

IP-016v1

Semiconductor IP & Design EnablementEnablingIC4–IC6 / M2–M3IC or manager

Also known as: PDK Release Manager; Design Enablement Release Manager; Design Kit Programme Manager; PDK QA Lead

See this role on the Process node lifecycle or on the PDK lifecycle or on the Photonics lifecycle or on the SoC lifecycle

Summary

Owns the assembly, qualification and controlled release of process design kits and design enablement collateral so that every internal and external design team is working from a consistent, validated, traceable technology view.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Plan and execute PDK release cycles from early-access through v1.0 production, aligning content to foundry technology milestones and design-team needs.
Assemble PDK components — SPICE models, techfiles, symbols and device generators, DRC/LVS/PEX runsets, design rule manual, ESD and reliability rules — into a coherent kit.
Run PDK qualification test suites, including device generator regressions, runset regression on golden test cases and tool-version compatibility matrices.
Manage version control, change control and release notes for the kit, with explicit deltas and known issues in every release.
Validate interoperability across Cadence Virtuoso, Synopsys Custom Compiler and Siemens tool chains, including OpenAccess and iPDK/interoperable views.
Triage design-team PDK issues, reproduce them against golden test cases and drive fixes with foundry or internal CAD owners.
Maintain the environment and module system so a design can be re-created bit-exactly on an older kit version years later.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Coordinate the digital design kit alongside the PDK — reference flows, standard cell and memory library drops, timing and RC corner definitions.
Control kit distribution, licensing and export compliance, and maintain an audit trail of who received which kit version.

Major tasks

Project

Produce and hand over the role's key deliverables
- Versioned PDK releases with release notes and known-issue list
- PDK qualification and regression test report per release
- Tool and version compatibility matrix
- Digital design kit drop with reference flows and library corners
- Kit distribution and access audit records
Support programsGeneral
- Agree what each program needs
- Deliver in time for milestones
Manage issuesGeneral
- Track requests to closure
- Escalate risks

Function

Run the functionGeneral
- Maintain policies and processes
- Keep records and controls
ImproveGeneral
- Report performance
- Lead improvement work

Works with

Typical backgrounds

BS/MS in Electrical Engineering or Microelectronics; 6–15 years in CAD, design enablement or physical verification; many arrive from custom layout, PV or library engineering roles.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

2 / 5

Remote feasibility

High

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Hsinchu, Bengaluru, Noida, San Jose, Hillsboro, Dresden, Grenoble, Shanghai, Seoul, Munich

Certifications / standards training

—

Transfers to (industries)

Limited; nearest transfer is engineering release management in CAD/CAE software and PLM environments

Risk if vacant

Design teams work from inconsistent or unqualified kits, producing silent DRC/LVS and model mismatches that are only discovered at tape-out or in silicon.

PDK & Design Kit Release Manager

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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