Customer Design Enablement

Stages

6. Test Chips & Yield Learning^DA
7. Customer Design Enablement (this stage)^A
8. Process Reliability Qualification^A

Business and customers milestones

• Design-start PDK release (DS)
• Pre-production PDK release (PP)
• First customer tape-outs (FT)
• Risk production start (RP)

Technology milestones

• Yield readiness (YR)
• Technology qualified (TQ) (technical readiness review TR3)

Disciplines

• Technology business and roadmap^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Investment tracked against the plan while the baseline and the design-start kit are built, and early customer interest gathered.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Customer agreements and risk production terms negotiated as product designs start on the pre-production kit.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Customer agreements and risk production terms negotiated as product designs start on the pre-production kit.
• Device engineering and modelling^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Devices characterised on the baseline flow and compact models fitted to its silicon for the design-start kit.; Models correlated to silicon
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Models extracted across corners and statistics and correlated to test chip silicon for the pre-production kit.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Models extracted across corners and statistics and correlated to test chip silicon for the pre-production kit.
• Lithography and patterning^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Hotspots learned from baseline and test chip wafers and fed back to the rules and OPC.
• Process module engineering^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Module specifications released into the frozen baseline and held under change control while the kit is fitted.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Modules supporting test chip, customer and qualification lots, with fixes going through baseline change control.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Modules supporting test chip, customer and qualification lots, with fixes going through baseline change control.
• Process integration^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Integrated flow and process baseline frozen, then integration learning run on test chip lots.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Integration issues closed and the process baseline released at technology qualification.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Integration issues closed and the process baseline released at technology qualification.
• Test chips and electrical test^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Test chips measured on the baseline flow, with parametric data feeding the models and yield learning.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Test chip results final and test structures monitored on customer and qualification lots.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Test chip results final and test structures monitored on customer and qualification lots.
• Yield, defects and process control^D
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Defect and yield learning run on test chip lots against the yield model.^DAA
  • Customer Design Enablement: maturity v0.9, Pre-production kit
• Process reliability and quality^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Reliability test plan written and early stress run on baseline test chips.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Technology qualification run and passed, with reliability design rules handed to the kit.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Technology qualification run and passed, with reliability design rules handed to the kit.^A; Qualification pass
• PDK development and release^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Design-start kit released with models fitted to baseline silicon and decks checked on test layouts.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Pre-production kit released with final rules and decks for product designs at an agreed risk.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Pre-production kit released with final rules and decks for product designs at an agreed risk.
• Foundation IP and libraries^O
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Foundation libraries handed over on the design-start kit and developed towards final.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Libraries final on the pre-production kit and validated on first customer silicon.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Libraries final on the pre-production kit and validated on first customer silicon.
• Customer design enablement and ecosystem^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Engagement continued on the design-start kit, with the reference flow and the shuttle plan in preparation.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Reference flow and shuttle schedule out, first customer tape-outs taken in and their product qualification planned.^O
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Reference flow and shuttle schedule out, first customer tape-outs taken in and their product qualification planned.
• Manufacturing operations and capacity^O
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Capacity plan tracked while the baseline and the kit mature, with no production commitment yet.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Fab readiness prepared alongside qualification and the capacity plan updated.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Fab readiness prepared alongside qualification and the capacity plan updated.
• Equipment and materials supply^A
  • Test Chips & Yield Learning: maturity v0.5, Design-start kit. Supplier readiness tracked as the frozen baseline is used on test chip lots.
  • Customer Design Enablement: maturity v0.9, Pre-production kit. Tools and materials qualified for production alongside technology qualification.
  • Process Reliability Qualification: maturity v0.9, Pre-production kit. Tools and materials qualified for production alongside technology qualification.