Partitioning a system into silicon: choosing compute, accelerator and memory blocks, NoC or AXI/CHI interconnect topology and QoS, address and memory map, clock, reset and power domain structure, and the IP reuse, chiplet and die-partitioning decisions that follow.
No statement on what tools can do has been recorded for this skill yet.
The Hub knows of no registered course, programme or certification for this skill yet.
Note from the research register: Grown from a strong RTL, performance or integration background into an architecture role over several SoC generations, learning by seeing prior choices validated or punished in silicon.
Register version 1.