Chip lifecycle / Test program lifecycle / Pre-silicon Test Program Build

Pre-silicon Test Program Build

Writing the test program before silicon exists: the test flow, test methods, levels, timing sets, pattern bursts, limits tables, bins and datalog setup, built in the tester's development environment, checked offline against the specification, and run where possible on the real tester and hardware with a loopback or reference part so that first silicon is not the first test of the program.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^D04 Pattern Generation & Conversion

^D05 Pre-silicon Test Program BuildYou are here

^A06 First Silicon Debug & Correlation

Product, test cost and quality milestones

Test engineering milestones

HRTest hardware ready PCPatterns converted and simulated TPRTest program ready for silicon FSFirst silicon on the tester CCCorrelation complete EREngineering test release

Test program management and cost^A

0.5

0.8

DFT architecture and test access^A

0.5

0.8

1.0

Test planning and specification^D

0.5

0.8

ATPG and pattern generation^D

0.5^D

0.8

1.0^A

Pattern conversion and simulation^D

0.5^D

0.8

1.0

Test program development^D

0.5

0.8^D

1.0^A

Probe card engineering^A

0.5

0.8

1.0

Load boards, sockets and handlers^A

0.5

0.8

1.0

Analog, mixed-signal and RF test^A

0.5

0.8^A

1.0

Characterisation and limits^A

0.5

0.8

Product engineering and yield^D

0.5

0.8

1.0^A

Test data and adaptive test^OO

0.3

0.5

Burn-in and system-level test^A

0.5

0.8

ATE platform and test operations^A

0.5

Test quality and escapes^O

0.3

0.5

Key0.0Planned0.3Early draft0.5Draft0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateYou are here: Pre-silicon Test Program BuildAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

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Stages

Pattern Generation & Conversion^D
Pre-silicon Test Program Build (this stage)^D
First Silicon Debug & Correlation^A

Product, test cost and quality milestones

Test engineering milestones

Disciplines

Test program management and cost^A
- Pattern Generation & Conversion: maturity 0.5, Draft. Hardware sets and tester time booked against the sample plan; the cost model updated with pattern counts and estimated test times.
- Pre-silicon Test Program Build: maturity 0.5, Draft. Hardware sets and tester time booked against the sample plan; the cost model updated with pattern counts and estimated test times.
- First Silicon Debug & Correlation: maturity 0.8, Feature complete. Engineering and qualification test releases run, with the cost model and the capacity plan on measured test times.
DFT architecture and test access^A
- Pattern Generation & Conversion: maturity 0.5, Draft. Test access checked in the netlist, and coverage on the final netlist confirmed with the simulated patterns in the DFT sign-off record; proof on the tester to come.
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Test access works end to end on the tester with the program and its hardware before silicon.
- First Silicon Debug & Correlation: maturity 1.0, Complete. Scan, compression, BIST and instruments proven on first silicon, with the findings fed back to design and the next product.
Test planning and specification^D
- Pattern Generation & Conversion: maturity 0.5, Draft. Coverage matrix and test flow filled in against the hardware specification and the pattern plan; open questions tracked.
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Specification matches the program built for silicon: every test coded with draft limits, the flow and binning plan complete; updated with first silicon findings.
- First Silicon Debug & Correlation: maturity 0.8, Feature complete. Specification matches the program built for silicon: every test coded with draft limits, the flow and binning plan complete; updated with first silicon findings.
ATPG and pattern generation^D
- Pattern Generation & Conversion: maturity 0.5, Draft. Every scan and memory BIST pattern set generated on the final netlist with the coverage recorded against the goal.^D
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Patterns running in the program on the tester with its hardware before silicon; fixes folded in.
- First Silicon Debug & Correlation: maturity 1.0, Complete. Patterns proven on first silicon with scan diagnosis working; compaction and reordering for test time follow.^A
Pattern conversion and simulation^D
- Pattern Generation & Conversion: maturity 0.5, Draft. Every pattern set converted to the tester format and clean in simulation with tester timing against the final netlist.^D
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Pattern bursts running in the program on the tester, with the release notes for the program build.
- First Silicon Debug & Correlation: maturity 1.0, Complete. Converted patterns passing on first silicon, with the fixes found in debug folded in.
Test program development^D
- Pattern Generation & Conversion: maturity 0.5, Draft. Main tests coded with converted patterns and running offline against simulation or a tester emulator; gaps tracked.
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Every test in the specification coded; the program runs end to end on the tester with its hardware and a reference before silicon.^D
- First Silicon Debug & Correlation: maturity 1.0, Complete. Released for its stage: correlated and released for engineering samples, then for qualification lots with limits from characterisation, then multi-site at the test time target.^A
Probe card engineering^A
- Pattern Generation & Conversion: maturity 0.5, Draft. Probe card built, inspected and checked out on the tester; spare and production sets ordered.
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Probe card proven with the program on the tester before silicon, with any fixes made.
- First Silicon Debug & Correlation: maturity 1.0, Complete. Probe card proven on first wafers, tuned for contact and signal quality; production sets follow.
Load boards, sockets and handlers^A
- Pattern Generation & Conversion: maturity 0.5, Draft. Load boards and sockets built, inspected and checked out on the tester and handler.
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Load boards and sockets proven with the program on the tester before silicon, with any fixes made.
- First Silicon Debug & Correlation: maturity 1.0, Complete. Load boards and sockets proven on first packaged parts and correlated; production sets follow.
Analog, mixed-signal and RF test^A
- Pattern Generation & Conversion: maturity 0.5, Draft. Analog and RF tests coded with their instrument set-ups and checked offline.
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Analog and RF methods in the program and running on the tester with its hardware before silicon.^A
- First Silicon Debug & Correlation: maturity 1.0, Complete. Bench to tester correlation done on first silicon; trim and calibration settings from characterisation follow.
Characterisation and limits^A
- Pattern Generation & Conversion: maturity 0.5, Draft. Characterisation programs, shmoo and corner set-ups and bench references ready for silicon.
- Pre-silicon Test Program Build: maturity 0.5, Draft. Characterisation programs, shmoo and corner set-ups and bench references ready for silicon.
- First Silicon Debug & Correlation: maturity 0.8, Feature complete. Early characterisation data from first silicon, with the correlation results to set guard bands against.
Product engineering and yield^D
- Pattern Generation & Conversion: maturity 0.5, Draft. Bench set-ups and expected values from simulation ready, with reference parts and data collection defined.
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Correlation report prepared with its parameters and tolerances, and the debug and data collection ready for first silicon.
- First Silicon Debug & Correlation: maturity 1.0, Complete. Correlation signed off: tester, bench, simulation and other testers agree, so yield learning, the yield model and the yield baseline run on trusted data.^A
Test data and adaptive test^OO
- Pattern Generation & Conversion: maturity 0.3, Early draft. Data pipeline from tester to database designed and built, with the datalog format checked on program runs.
- Pre-silicon Test Program Build: maturity 0.5, Draft. Datalogs and failure capture working with the program, and data from first silicon flowing to product engineering.
- First Silicon Debug & Correlation: maturity 0.5, Draft. Datalogs and failure capture working with the program, and data from first silicon flowing to product engineering.
Burn-in and system-level test^A
- Pattern Generation & Conversion: maturity 0.5, Draft. Burn-in boards built and checked out; system-level test boards and content under way.
- Pre-silicon Test Program Build: maturity 0.8, Feature complete. Burn-in and system-level test content ready and run on the boards before silicon, then on first parts.
- First Silicon Debug & Correlation: maturity 0.8, Feature complete. Burn-in and system-level test content ready and run on the boards before silicon, then on first parts.
ATE platform and test operations^A
- Pattern Generation & Conversion: maturity 0.5, Draft. Tester time, debug stations and data collection ready for the program build, first silicon and engineering samples.
- Pre-silicon Test Program Build: maturity 0.5, Draft. Tester time, debug stations and data collection ready for the program build, first silicon and engineering samples.
- First Silicon Debug & Correlation: maturity 0.5, Draft. Tester time, debug stations and data collection ready for the program build, first silicon and engineering samples.
Test quality and escapes^O
- Pattern Generation & Conversion: maturity 0.3, Early draft. Quality requirements traced into the coverage matrix and the screening plan, with coverage gaps listed with their risk.
- Pre-silicon Test Program Build: maturity 0.5, Draft. Coverage and screening risks reviewed on the program before silicon and on the engineering release before samples ship.
- First Silicon Debug & Correlation: maturity 0.5, Draft. Coverage and screening risks reviewed on the program before silicon and on the engineering release before samples ship.

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