First Silicon Debug & Correlation

Disciplines

• Test program management and cost^A
  • Pre-silicon Test Program Build: maturity 0.5, Draft. Hardware sets and tester time booked against the sample plan; the cost model updated with pattern counts and estimated test times.
  • First Silicon Debug & Correlation: maturity 0.8, Feature complete. Engineering and qualification test releases run, with the cost model and the capacity plan on measured test times.
  • Characterisation & Limit Setting: maturity 0.8, Feature complete. Engineering and qualification test releases run, with the cost model and the capacity plan on measured test times.
• DFT architecture and test access^A
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Test access works end to end on the tester with the program and its hardware before silicon.
  • First Silicon Debug & Correlation: maturity 1.0, Complete. Scan, compression, BIST and instruments proven on first silicon, with the findings fed back to design and the next product.
• Test planning and specification^D
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Specification matches the program built for silicon: every test coded with draft limits, the flow and binning plan complete; updated with first silicon findings.
  • First Silicon Debug & Correlation: maturity 0.8, Feature complete. Specification matches the program built for silicon: every test coded with draft limits, the flow and binning plan complete; updated with first silicon findings.
  • Characterisation & Limit Setting: maturity 1.0, Complete. Production limits from characterisation in the specification and the coverage matrix final at the limits freeze.
• ATPG and pattern generation^D
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Patterns running in the program on the tester with its hardware before silicon; fixes folded in.
  • First Silicon Debug & Correlation: maturity 1.0, Complete. Patterns proven on first silicon with scan diagnosis working; compaction and reordering for test time follow.^A
  • Characterisation & Limit Setting: maturity 1.0, Complete. Patterns proven on first silicon with scan diagnosis working; compaction and reordering for test time follow.
• Pattern conversion and simulation^D
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Pattern bursts running in the program on the tester, with the release notes for the program build.
  • First Silicon Debug & Correlation: maturity 1.0, Complete. Converted patterns passing on first silicon, with the fixes found in debug folded in.
• Test program development^D
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Every test in the specification coded; the program runs end to end on the tester with its hardware and a reference before silicon.^D
  • First Silicon Debug & Correlation: maturity 1.0, Complete. Released for its stage: correlated and released for engineering samples, then for qualification lots with limits from characterisation, then multi-site at the test time target.^A
  • Characterisation & Limit Setting: maturity 1.0, Complete. Released for its stage: correlated and released for engineering samples, then for qualification lots with limits from characterisation, then multi-site at the test time target.
• Probe card engineering^A
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Probe card proven with the program on the tester before silicon, with any fixes made.
  • First Silicon Debug & Correlation: maturity 1.0, Complete. Probe card proven on first wafers, tuned for contact and signal quality; production sets follow.
  • Characterisation & Limit Setting: maturity 1.0, Complete. Probe card proven on first wafers, tuned for contact and signal quality; production sets follow.
• Load boards, sockets and handlers^A
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Load boards and sockets proven with the program on the tester before silicon, with any fixes made.
  • First Silicon Debug & Correlation: maturity 1.0, Complete. Load boards and sockets proven on first packaged parts and correlated; production sets follow.
  • Characterisation & Limit Setting: maturity 1.0, Complete. Load boards and sockets proven on first packaged parts and correlated; production sets follow.
• Analog, mixed-signal and RF test^A
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Analog and RF methods in the program and running on the tester with its hardware before silicon.^A
  • First Silicon Debug & Correlation: maturity 1.0, Complete. Bench to tester correlation done on first silicon; trim and calibration settings from characterisation follow.
  • Characterisation & Limit Setting: maturity 1.0, Complete. Bench to tester correlation done on first silicon; trim and calibration settings from characterisation follow.
• Characterisation and limits^A
  • Pre-silicon Test Program Build: maturity 0.5, Draft. Characterisation programs, shmoo and corner set-ups and bench references ready for silicon.
  • First Silicon Debug & Correlation: maturity 0.8, Feature complete. Early characterisation data from first silicon, with the correlation results to set guard bands against.
  • Characterisation & Limit Setting: maturity 1.0, Complete. Characterisation complete across corners, voltage and temperature, with production limits and guard bands set at the limits freeze.^A; Test limits baselined (milestone for one item)
• Product engineering and yield^D
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Correlation report prepared with its parameters and tolerances, and the debug and data collection ready for first silicon.
  • First Silicon Debug & Correlation: maturity 1.0, Complete. Correlation signed off: tester, bench, simulation and other testers agree, so yield learning, the yield model and the yield baseline run on trusted data.^A
  • Characterisation & Limit Setting: maturity 1.0, Complete. Correlation signed off: tester, bench, simulation and other testers agree, so yield learning, the yield model and the yield baseline run on trusted data.
• Test data and adaptive test^OO
  • Pre-silicon Test Program Build: maturity 0.5, Draft. Datalogs and failure capture working with the program, and data from first silicon flowing to product engineering.
  • First Silicon Debug & Correlation: maturity 0.5, Draft. Datalogs and failure capture working with the program, and data from first silicon flowing to product engineering.
  • Characterisation & Limit Setting: maturity 0.8, Feature complete. Outlier screening and adaptive test rules drafted from characterisation data and the test removal analysis.
• Burn-in and system-level test^A
  • Pre-silicon Test Program Build: maturity 0.8, Feature complete. Burn-in and system-level test content ready and run on the boards before silicon, then on first parts.
  • First Silicon Debug & Correlation: maturity 0.8, Feature complete. Burn-in and system-level test content ready and run on the boards before silicon, then on first parts.
  • Characterisation & Limit Setting: maturity 1.0, Complete. Burn-in recipe released for the qualification lots, with the system-level test content proven; reductions follow.
• ATE platform and test operations^A
  • Pre-silicon Test Program Build: maturity 0.5, Draft. Tester time, debug stations and data collection ready for the program build, first silicon and engineering samples.
  • First Silicon Debug & Correlation: maturity 0.5, Draft. Tester time, debug stations and data collection ready for the program build, first silicon and engineering samples.
  • Characterisation & Limit Setting: maturity 0.8, Feature complete. Production test sites and capacity prepared, with qualification lots run at the site and the transfer package drafted.
• Test quality and escapes^O
  • Pre-silicon Test Program Build: maturity 0.5, Draft. Coverage and screening risks reviewed on the program before silicon and on the engineering release before samples ship.
  • First Silicon Debug & Correlation: maturity 0.5, Draft. Coverage and screening risks reviewed on the program before silicon and on the engineering release before samples ship.
  • Characterisation & Limit Setting: maturity 0.8, Feature complete. Qualification release reviewed, with known gaps, outlier screens and proposed test removals assessed for escape risk.