Chip lifecycle / FPGA lifecycle / Simulation & Verification

Simulation & Verification

Closing verification on the complete logic in simulation, with clock domain crossing and lint checks and the fixes they lead to, before it is built for hardware, where debugging is slower.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A04 Design Code Completion

^D05 Simulation & VerificationYou are here

^A06 Synthesis, Place & Route & Timing Closure

Product milestones

FPGA design milestones

BRBoard released for build DCDesign code complete VSVerification sign-off TCTiming closure and bitstream

System architecture^AAO

0.8

1.0

FPGA logic design^DAAAO

0.8^A

1.0

Freeze^AO

FPGA verification^DA

0.8

1.0^DA

Implementation and timing closure^AA

1.0^AA

Embedded software and drivers^DA

0.5

0.8

Board bring-up and debug^A

0.3

0.5

0.8

System validation and compliance^A

0.3

0.5

Configuration security^A

0.5

0.8^A

Production and supply^A

0.3

0.5

Product management^AO

0.5

0.8

Key0.0Planned0.3Early draft0.5Draft0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateYou are here: Simulation & VerificationAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

Show this chart as a list

Stages

Design Code Completion^A
Simulation & Verification (this stage)^D
Synthesis, Place & Route & Timing Closure^A

Product milestones

FPGA design milestones

Disciplines

System architecture^AAO
- Design Code Completion: maturity 0.8, Feature complete. Architecture matches the complete design code; only clarifications remain.
- Simulation & Verification: maturity 1.0, Complete. Architecture confirmed against the verified logic.
FPGA logic design^DAAAO
- Design Code Completion: maturity 0.8, Feature complete. All planned logic written, integrated and reviewed; fixes for the bugs verification finds continue.^A
- Simulation & Verification: maturity 1.0, Complete. Logic signed off with verification, with bugs fixed or waived and the timing constraints final.
- Synthesis, Place & Route & Timing Closure: maturity Freeze, Frozen. Source frozen for the bitstream build; fixes, such as those found on the board, go through change control.^AO; Design code freeze
FPGA verification^DA
- Design Code Completion: maturity 0.8, Feature complete. Environment complete at design code complete. Results: regressions and coverage closure under way on the complete code, with bugs going back to design.
- Simulation & Verification: maturity 1.0, Complete. Results: coverage goals met, clock domain crossing checks clean or waived, and open bugs fixed or waived; every later fix is regressed.^DA
Implementation and timing closure^AA
- Design Code Completion: maturity 0.5, Draft. Trial builds of the complete design track utilisation and timing against the agreed headroom.
- Simulation & Verification: maturity 0.8, Feature complete. Timing closure under way on the near-final source, with the constraints in review.
- Synthesis, Place & Route & Timing Closure: maturity 1.0, Complete. Every timing constraint met and the bitstream built from the frozen, signed-off source, with the power estimate taken from the routed design.^A
Board design^AA
- Design Code Completion: maturity 0.8, Feature complete. First boards fabricated and assembled, with bare-board and power-up checks run.
- Simulation & Verification: maturity 1.0, Complete. Boards checked out with test designs: rails, clocks, memories and interfaces work, ready for the product bitstream.
- Synthesis, Place & Route & Timing Closure: maturity Freeze, Frozen. Board revision frozen for bring-up and validation; changes need a new revision under change control.; Board revision frozen
Embedded software and drivers^DA
- Design Code Completion: maturity 0.5, Draft. Drivers and board support package written against the complete design code and run in co-simulation or on a development board.
- Simulation & Verification: maturity 0.5, Draft. Drivers and board support package written against the complete design code and run in co-simulation or on a development board.
- Synthesis, Place & Route & Timing Closure: maturity 0.8, Feature complete. Drivers, board support package and boot code ready for the first boards, built against the timing-clean bitstream.
Board bring-up and debug^A
- Design Code Completion: maturity 0.3, Early draft. Bring-up approach drafted once the board is released, with lab equipment and debug access planned.
- Simulation & Verification: maturity 0.5, Draft. Lab ready and the first boards checked out with the board team; test bitstreams and scripts in preparation.
- Synthesis, Place & Route & Timing Closure: maturity 0.8, Feature complete. Bring-up plan final, with test bitstreams, on-chip analyser set-ups and scripts ready for the product bitstream.
System validation and compliance^A
- Design Code Completion: maturity 0.3, Early draft. System test plan drafted from the requirements, with test equipment and compliance laboratories arranged.
- Simulation & Verification: maturity 0.3, Early draft. System test plan drafted from the requirements, with test equipment and compliance laboratories arranged.
- Synthesis, Place & Route & Timing Closure: maturity 0.5, Draft. System test plan reviewed and test set-ups ready for the first integrated boards.
Configuration security^A
- Design Code Completion: maturity 0.5, Draft. Secure boot, bitstream encryption and authentication, and the field update scheme designed with the logic and software teams.
- Simulation & Verification: maturity 0.5, Draft. Secure boot, bitstream encryption and authentication, and the field update scheme designed with the logic and software teams.
- Synthesis, Place & Route & Timing Closure: maturity 0.8, Feature complete. Encryption and authentication settings in the bitstream build; secure configuration and the update route tried on the board.^A
Production and supply^A
- Design Code Completion: maturity 0.3, Early draft. Board components checked for availability and manufacturability, with a first approved component list at board release.
- Simulation & Verification: maturity 0.5, Draft. Production programming method and manufacturing test approach agreed, using the test and programming access designed into the board.
- Synthesis, Place & Route & Timing Closure: maturity 0.5, Draft. Production programming method and manufacturing test approach agreed, using the test and programming access designed into the board.
Product management^AO
- Design Code Completion: maturity 0.5, Draft. Product plan confirmed against the complete design and the board cost, with customers and the launch window agreed.
- Simulation & Verification: maturity 0.5, Draft. Product plan confirmed against the complete design and the board cost, with customers and the launch window agreed.
- Synthesis, Place & Route & Timing Closure: maturity 0.8, Feature complete. Launch, support and field update plans drafted against the timing-clean bitstream and the bring-up results.

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