Reviews the FPGA verification plan before it is made final. The verification lead runs it with the FPGA design lead and the system hardware architect.
MustThe material under review is a tagged version, named in the record.
MustReviewers received the material and this checklist early enough to prepare.
ShouldAt least one reviewer did not take part in the work under review.
ShouldThe scope of the review and anything excluded are stated at the start.
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