1. Purpose and scope
This stage turns a first integrated design into a complete one. When it ends, every planned feature exists in reviewed form, so that verification can close coverage on the real design rather than chasing a moving one, and implementation can start closing timing on paths that will not change shape. The logic is feature complete here, not finished: bugs found by verification are expected and are fixed in the next stage, each with a review and a regression run.
Design and verification move together through the stage. The verification environment has been built alongside the logic since the architecture, so as each feature lands its tests already exist or follow within days. By the end of the stage the testbench runs the top-level design with every IP core or its model, and the verification plan is final.
The board is being fabricated and assembled while this stage runs, which gives it a fixed partner on the outside. The pin assignment, the configuration connections and the power budget were committed with the board release, so changes that touch them now cost a board rework or a revision. The stage is where that discipline is tested: features must fit the pins and the power the board already has.
In scope: the remaining features, full integration of the IP cores and the processor subsystem, the register map checked against the software interface, code review and lint of every block, timing constraints for every clock and external interface, trial builds of the full design, and the evidence for the Design code complete gate. Out of scope: coverage closure and sign-off, which happen in Simulation & Verification, and final timing closure, which happens in Synthesis, Place & Route & Timing Closure.
12 more sections for registered members.