Design Code Completion: exit checklist

1. FPGA design

• MustAll planned features are implemented in the FPGA design source.

  Evidence

  Feature status against the architecture

  Owner

  FPGA design lead

• MustCode review is complete for every block, with findings closed or tracked.

  Evidence

  Code review records

  Owner

  FPGA design lead

• MustTiming constraints exist for every clock and every external interface, in their initial form.

  Evidence

  FPGA timing constraints

  Owner

  FPGA design engineer

• MustTrial implementation results show the design fits and give a first view of timing.

  Evidence

  Trial implementation results

  Owner

  FPGA implementation engineer