Developing the FPGA device itself, as the vendor does: from the device family plan and the programmable fabric architecture of logic blocks and routing, through the hard IP, the configuration logic and bitstream security, tile design, verification and tape-out, to silicon characterisation, speed grades, the timing data in the vendor's place-and-route software, qualification and the roll-out of the rest of the family. The vendor's design software is developed alongside the silicon, because no customer can use the device without it.
Start here: what it is, how the related terms differ, what this lifecycle covers and its phases in order, then the detail.
A field programmable gate array, or FPGA, is a chip whose logic is defined after manufacture. It holds a fabric of logic blocks, block memories and arithmetic blocks joined by programmable routing, and a configuration memory that sets what every block and switch does. Loading a bitstream turns the same silicon into a different circuit.
Most devices also carry hard IP beside the fabric, such as high-speed transceivers, memory interfaces and sometimes processor cores, because fixed blocks do those jobs in less area and power.
An FPGA is sold as a family of densities, packages and grades on one architecture, and is used through the vendor's design software, which maps a customer's design onto the fabric, times it and produces the bitstream. Silicon and software are developed and released together.
The FPGA device beside other programmable and custom silicon, and the terms for what the vendor releases:
| Term | What it is | How it differs |
|---|---|---|
| CPLD | Complex programmable logic device: a small programmable chip with a few wide logic blocks, usually with non-volatile configuration. | Smaller and simpler than an FPGA, often used for glue logic. |
| FPGA |
FPGA chip development lifecycle: 13 stages, 17 gates of its own and 7 hand-offs to the Product lifecycle, from Device Family Definition to Software Releases, Long-term Supply & End of Life.
13 stages, 17 gates of its own and 7 hand-offs to the Product lifecycle, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
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A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Deciding what the device family is for: the markets and applications it serves, the range of densities from the smallest to the largest member, the hard IP it carries, the package options, the speed grades and temperature grades, the process technology and how long the family will be supplied.
Concept approval gate, owned by the Product lifecycle (Concept approval)Family requirements baselined gate
Choosing the programmable fabric: the logic block and its look-up tables, carry chains and registers, the routing architecture and its switch patterns, the block memories, the arithmetic blocks, the clock network and the input and output structure.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
Choosing the fixed function blocks built into the device beside the fabric, such as high-speed transceivers, memory interfaces, PCI Express and Ethernet controllers, processor subsystems and arithmetic engines, deciding which are designed in-house and which are licensed, and planning how each connects to the fabric, the clock network and the configuration logic.
Designing how the device is programmed and protected: the configuration memory, the controller that loads the bitstream from external memory or a host, the bitstream format, partial reconfiguration where offered, readback and error detection in the configuration memory, and the security features that encrypt and authenticate the bitstream, store keys and respond to tampering.
Designing the repeating tiles that make up the fabric, with their logic, routing switches and configuration cells, largely as custom circuits because the same tile is repeated many times, and assembling the device RTL and netlists from tiles and hard IP, with the verification environment built alongside, until every planned feature is in at the tile and RTL freeze.
Closing verification on the frozen tiles and device RTL: running the regressions, closing functional and code coverage for the fabric, the configuration logic, the security features and the hard IP connections, simulating the device programmed with real bitstreams, and fixing or waiving every open bug before verification signs off.
Adding the new device to the vendor's design software: the device model, synthesis and packing onto its logic blocks, placement, routing, timing analysis, power estimation and bitstream generation.
Building the full device layout from tiles, hard IP, clock and power networks and the input and output ring, closing timing, power integrity and the physical checks, and releasing the first family member to manufacture.
Powering up first silicon, loading the first bitstreams, bringing up the configuration logic, the security features and each hard IP block, then characterising the fabric and the hard IP across voltage, temperature and process corners to measure the delays the timing models need.
First silicon gateFirst designs running on silicon gateSilicon characterised gate
Setting the speed grades and temperature grades the family is sold in from characterisation and the spread of production silicon, writing the binning tests that sort parts into them, and releasing the timing data in the design software, which typically moves from advance and preliminary data to production data as silicon is measured.
Engineering samples gate, owned by the Product lifecycle (Engineering samples)Speed grades and production timing data released gate
Qualifying the device and its packages for reliability, including the configuration memory and the security features, releasing the production test program that tests the fabric through many test configurations, and releasing the family member for volume orders.
Qualification start gateQualification passed gateTR3, technical readiness reviewProduction release gate, owned by the Product lifecycle (Production release)
Releasing the rest of the family: further densities, package options and temperature grades, such as industrial, automotive or defence grades, each with its own timing data, test program and qualification, often by similarity to the first member, and ramping supply.
Volume ramp gate, owned by the Product lifecycle (Volume ramp)Family member released gate
Keeping the family usable for the long service lives many FPGA customers need: regular software releases that fix timing and tool issues, errata updates, supply and quality control, and finally a discontinuance with a last-time buy and an archive of the design, test and timing data.
Maintenance software release gateLast-time buy gate, owned by the Product lifecycle (Last-time buy)Last-time ship gate, owned by the Product lifecycle (Last-time ship)
| A chip with a programmable fabric of logic, memory and routing, configured by a bitstream. |
| The device this lifecycle develops; its function is set by each customer. |
| SoC FPGA | An FPGA with hard processor cores and their peripherals on the same die. | Adds a processor subsystem as hard IP, so the vendor also supplies its boot and software support. |
|---|
| eFPGA | Embedded FPGA: programmable fabric licensed as IP and built into another chip. | Sold as IP for an SoC, not as a packaged device with its own family. |
|---|
| Structured ASIC | A pre-built base array customised for one design in a few metal or via layers. | Fixed at manufacture for one customer; cannot be reprogrammed. |
|---|
| ASIC | A chip designed for one customer or application, with every layer custom. | Lowest unit cost at volume, but the design is fixed at tape-out. |
|---|
| FPGA-based product | A board or system whose function is a design loaded into a commercial FPGA. | Built by the vendor's customers, in the separate FPGA design lifecycle. |
|---|
| Device family and family member | Devices on one architecture, and one of them with its density, package and grade. | Each member has its own timing data, test program and qualification. |
|---|
| Speed grade | The speed class a part is sorted into by test and sold as. | Customers design to the grade's timing data, a promise about every part sold in it. |
|---|
| Bitstream | The configuration data the design software generates and the device loads. | The customer's design in loadable form; the vendor defines its format and protection. |
|---|
The FPGA device lifecycle is the vendor's path for one device family: defining it, choosing the fabric, building in hard IP and configuration and security logic, designing the tiles, adding the device to the design software, taping out, characterising silicon, setting speed grades, qualifying, then releasing the rest of the family and supporting it for many years.
It differs from the FPGA design lifecycle, in which a customer builds a product on a commercial device. Here the fabric is the design, and its quality shows only through how well the software maps customers' designs onto it.
A product line manager usually owns the family, with a chief architect owning the fabric and a software lead owning its support in the design software.
Gates matter because the fabric cannot change after tape-out and the timing data reaches every customer design. Architecture freezes, pre-silicon software readiness and the release of production timing data find problems while they are cheap to fix.
A dotted underline opens the full definition in the glossary.
Credible sources, named for further reading. Standards are available from the body that publishes them.
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