Configuration & Bitstream Security

Disciplines

• Family planning and product marketing^A
  • Hard IP Selection & Integration: maturity 0.3, Early draft. Product plan agreed: member order, software scope, target cost and schedule committed, with the roadmap drafted.
  • Configuration & Bitstream Security: maturity 0.5, Draft. Launch plan drafted against the configuration and tile designs: pricing approach, lead customers and development kit scope.
  • Tile Design & RTL: maturity 0.5, Draft. Launch plan drafted against the configuration and tile designs: pricing approach, lead customers and development kit scope.
• Fabric architecture^A
  • Hard IP Selection & Integration: maturity 0.5, Draft. Device floorplan agreed with the hard IP placed and the configuration logic fitted around the fabric columns.
  • Configuration & Bitstream Security: maturity 0.5, Draft. Device floorplan agreed with the hard IP placed and the configuration logic fitted around the fabric columns.
  • Tile Design & RTL: maturity 0.8, Feature complete. Tiles and device RTL reviewed against the architecture at the tile and RTL freeze.
• Hard IP integration^O
  • Hard IP Selection & Integration: maturity 0.5, Draft. Every block selected with a source, a version and an integration specification, placed in the floorplan.^O
  • Configuration & Bitstream Security: maturity 0.5, Draft. Every block selected with a source, a version and an integration specification, placed in the floorplan.
  • Tile Design & RTL: maturity 0.8, Feature complete. Hard IP connected to the fabric, clocks and configuration logic in the frozen device RTL.
• Configuration and bitstream security^O
  • Hard IP Selection & Integration: maturity 0.3, Early draft. Configuration memory concept chosen; controller, bitstream format and security features outlined.
  • Configuration & Bitstream Security: maturity 0.5, Draft. Configuration and security architecture frozen, with the bitstream format agreed with the software team.^O; Bitstream format freeze (milestone for one item)
  • Tile Design & RTL: maturity 0.8, Feature complete. Controller, configuration cells and security features designed into the frozen device RTL.
• Tile and circuit design^D
  • Hard IP Selection & Integration: maturity 0.3, Early draft. Logic, routing and memory tile circuits explored on the frozen fabric architecture, with first cell choices.^A
  • Configuration & Bitstream Security: maturity 0.5, Draft. Configuration and switch cells designed and the main tiles drawn and simulated across corners.^A
  • Tile Design & RTL: maturity 0.8, Feature complete. Every planned tile and device feature in, at the tile and RTL freeze; only reviewed fixes from here.
• Device verification^A
  • Hard IP Selection & Integration: maturity 0.3, Early draft. Environment: verification plan drafted from the frozen fabric architecture; testbench, bitstream-driven tests and coverage model planned.
  • Configuration & Bitstream Security: maturity 0.5, Draft. Environment: testbench and checkers running on the first tile and device RTL drops, with the configuration logic modelled.^A
  • Tile Design & RTL: maturity 0.8, Feature complete. Environment complete at the tile and RTL freeze. Results: regressions and coverage closure under way, with bugs going back to design.^A
• Physical design and tape-out^A
  • Hard IP Selection & Integration: maturity 0.0, Planned. Die size, fabric column pattern and hard IP placement options assessed with the architects for the integration plan; no floorplan started.
  • Configuration & Bitstream Security: maturity 0.3, Early draft. Full device floorplan started from the agreed hard IP placement and fabric columns.
  • Tile Design & RTL: maturity 0.5, Draft. Device floorplan final at the tile and RTL freeze, with clock, power and input and output ring planned.
• Test and test configurations^A
  • Configuration & Bitstream Security: maturity 0.0, Planned. Test approach outlined: fabric tested through test configurations, hard IP through scan and built-in self-test.
  • Tile Design & RTL: maturity 0.3, Early draft. Test strategy final at the tile and RTL freeze, with fabric, memory and hard IP coverage targets.
• Place-and-route and timing software^O
  • Hard IP Selection & Integration: maturity 0.3, Early draft. Experimental flow maps the benchmark designs onto candidate fabrics; device model started on the frozen architecture.
  • Configuration & Bitstream Security: maturity 0.5, Draft. Device model, packing, placement and routing running on the new fabric; bitstream generator started on the frozen format.
  • Tile Design & RTL: maturity 0.5, Draft. Device model, packing, placement and routing running on the new fabric; bitstream generator started on the frozen format.
• Silicon bring-up and validation^A
  • Tile Design & RTL: maturity 0.0, Planned. Debug and observability needs for first silicon agreed with the designers before the tile and RTL freeze, such as configuration readback and access to the hard IP; no bring-up plan yet.
• Characterisation and speed grades^A
  • Tile Design & RTL: maturity 0.0, Planned. Delay measurement structures and on-chip monitors asked of the tile designers before the tile and RTL freeze; corners and material not yet planned.
• Foundry, packaging and supply^A
  • Hard IP Selection & Integration: maturity 0.3, Early draft. Process, configuration memory technology and package options assessed for technology feasibility.
  • Configuration & Bitstream Security: maturity 0.5, Draft. Process design kit version and package technology chosen for the first member, with the package design started.
  • Tile Design & RTL: maturity 0.5, Draft. Process design kit version and package technology chosen for the first member, with the package design started.